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User fields on C channel #2632

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merged 3 commits into from
Sep 10, 2020
Merged

User fields on C channel #2632

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bf225c0
tilelink: add user bits to the C channel
terpstra Sep 9, 2020
979a45d
CacheCork: don't hardcode AMBAProt; use the masters values
terpstra Sep 9, 2020
3497cf8
DCache: providing AMBAProt on C channel is now the cache's responsibi…
terpstra Sep 9, 2020
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10 changes: 10 additions & 0 deletions src/main/scala/rocket/DCache.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -734,6 +734,16 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val newCoh = Wire(init = probeNewCoh)
releaseWay := s2_probe_way

tl_out_c.bits.user.lift(AMBAProt).foreach { x =>
x.fetch := false.B
x.secure := true.B
x.privileged := true.B
x.bufferable := true.B
x.modifiable := true.B
x.readalloc := true.B
x.writealloc := true.B
}

if (!usingDataScratchpad) {
when (s2_victimize) {
assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack)
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2 changes: 2 additions & 0 deletions src/main/scala/tilelink/Bundles.scala
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Expand Up @@ -212,6 +212,8 @@ final class TLBundleC(params: TLBundleParameters)
val size = UInt(width = params.sizeBits)
val source = UInt(width = params.sourceBits) // from
val address = UInt(width = params.addressBits) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(width = params.dataBits)
val corrupt = Bool() // only applies to *Data messages
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11 changes: 1 addition & 10 deletions src/main/scala/tilelink/CacheCork.scala
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Expand Up @@ -6,7 +6,6 @@ import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.amba.AMBAProt
import scala.math.{min,max}
import TLMessages._

Expand Down Expand Up @@ -92,15 +91,7 @@ class TLCacheCork(unsafe: Boolean = false, sinkIds: Int = 8)(implicit p: Paramet
lgSize = in.c.bits.size,
data = in.c.bits.data,
corrupt = in.c.bits.corrupt)._2
c_a.bits.user.lift(AMBAProt).foreach { x =>
x.fetch := false.B
x.secure := true.B
x.privileged := true.B
x.bufferable := true.B
x.modifiable := true.B
x.readalloc := true.B
x.writealloc := true.B
}
c_a.bits.user :<= in.c.bits.user

// Releases without Data succeed instantly
val c_d = Wire(in.d)
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