Enable ProcedureSyntax lint rule

.scalafix.conf

@@ -3,4 +3,5 @@ rules = [
   DisableSyntax,
   NoAutoTupling,
   NoValInForComprehension,
+  ProcedureSyntax,
 ]

src/main/scala/amba/ahb/Bundles.scala

@@ -37,7 +37,7 @@ class AHBSlaveBundle(val params: AHBBundleParameters) extends Bundle
   val hmaster   = if (params.lite) None else Some(UInt(OUTPUT, width = 4))
   val hsplit    = if (params.lite) None else Some(UInt(INPUT, width = 16))
 
-  def tieoff() {
+  def tieoff(): Unit = {
     hrdata.dir match {
       case INPUT =>
         hreadyout := Bool(false)
@@ -94,7 +94,7 @@ class AHBMasterBundle(val params: AHBBundleParameters) extends Bundle
   val hresp   = UInt(INPUT, width = params.hrespBits)
   val hrdata  = UInt(INPUT, width = params.dataBits)
 
-  def tieoff() {
+  def tieoff(): Unit = {
     hrdata.dir match {
       case INPUT =>
         hgrant.foreach { _ := Bool(false) }

src/main/scala/amba/ahb/Nodes.scala

@@ -16,7 +16,7 @@ object AHBImpSlave extends SimpleNodeImp[AHBMasterPortParameters, AHBSlavePortPa
   def bundle(e: AHBEdgeParameters) = AHBSlaveBundle(e.bundle)
   def render(e: AHBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.slave.beatBytes * 8).toString)
 
-  override def monitor(bundle: AHBSlaveBundle, edge: AHBEdgeParameters) {
+  override def monitor(bundle: AHBSlaveBundle, edge: AHBEdgeParameters): Unit = {
     edge.params.lift(AHBSlaveMonitorBuilder).foreach { builder =>
       val monitor = Module(builder(AHBSlaveMonitorArgs(edge)))
       monitor.io.in := bundle
@@ -38,7 +38,7 @@ object AHBImpMaster extends SimpleNodeImp[AHBMasterPortParameters, AHBSlavePortP
   def bundle(e: AHBEdgeParameters) = AHBMasterBundle(e.bundle)
   def render(e: AHBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label = (e.slave.beatBytes * 8).toString)
 
-  override def monitor(bundle: AHBMasterBundle, edge: AHBEdgeParameters) {
+  override def monitor(bundle: AHBMasterBundle, edge: AHBEdgeParameters): Unit = {
     edge.params.lift(AHBMasterMonitorBuilder).foreach { builder =>
       val monitor = Module(builder(AHBMasterMonitorArgs(edge)))
       monitor.io.in := bundle

src/main/scala/amba/ahb/RegisterRouter.scala

@@ -116,5 +116,5 @@ trait HasAHBControlRegMap { this: RegisterRouter =>
     executable = executable)
 
   // Internally, this function should be used to populate the control port with registers
-  protected def regmap(mapping: RegField.Map*) { controlNode.regmap(mapping:_*) }
+  protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
 }

src/main/scala/amba/apb/Bundles.scala

@@ -25,7 +25,7 @@ class APBBundle(val params: APBBundleParameters) extends Bundle
   val prdata    = UInt(INPUT, width = params.dataBits)
   val pduser    = BundleMap(params.responseFields)
 
-  def tieoff() {
+  def tieoff(): Unit = {
     pready.dir match {
       case INPUT =>
         pready  := Bool(false)

src/main/scala/amba/apb/Nodes.scala

@@ -15,7 +15,7 @@ object APBImp extends SimpleNodeImp[APBMasterPortParameters, APBSlavePortParamet
   def bundle(e: APBEdgeParameters) = APBBundle(e.bundle)
   def render(e: APBEdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, (e.slave.beatBytes * 8).toString)
 
-  override def monitor(bundle: APBBundle, edge: APBEdgeParameters) {
+  override def monitor(bundle: APBBundle, edge: APBEdgeParameters): Unit = {
     edge.params.lift(APBMonitorBuilder).foreach { builder =>
       val monitor = Module(builder(APBMonitorArgs(edge)))
       monitor.io.in := bundle

src/main/scala/amba/apb/RegisterRouter.scala

@@ -97,5 +97,5 @@ trait HasAPBControlRegMap { this: RegisterRouter =>
     executable = executable)
 
   // Internally, this function should be used to populate the control port with registers
-  protected def regmap(mapping: RegField.Map*) { controlNode.regmap(mapping:_*) }
+  protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
 }

src/main/scala/amba/axi4/Bundles.scala

@@ -75,7 +75,7 @@ class AXI4Bundle(params: AXI4BundleParameters) extends AXI4BundleBase(params)
   val ar = Irrevocable(new AXI4BundleAR(params))
   val r  = Irrevocable(new AXI4BundleR (params)).flip
 
-  def tieoff() {
+  def tieoff(): Unit = {
     ar.ready.dir match {
       case INPUT =>
         ar.ready := Bool(false)

src/main/scala/amba/axi4/Delayer.scala

@@ -15,7 +15,7 @@ class AXI4Delayer(q: Double)(implicit p: Parameters) extends LazyModule
   require (0.0 <= q && q < 1)
 
   lazy val module = new LazyModuleImp(this) {
-    def feed[T <: Data](sink: IrrevocableIO[T], source: IrrevocableIO[T], noise: T) {
+    def feed[T <: Data](sink: IrrevocableIO[T], source: IrrevocableIO[T], noise: T): Unit = {
       // irrevocable requires that we not lower valid
       val hold = RegInit(Bool(false))
       when (sink.valid)  { hold := Bool(true) }
@@ -28,7 +28,7 @@ class AXI4Delayer(q: Double)(implicit p: Parameters) extends LazyModule
       when (!sink.valid) { sink.bits := noise }
     }
 
-    def anoise[T <: AXI4BundleA](bits: T) {
+    def anoise[T <: AXI4BundleA](bits: T): Unit = {
       bits.id    := LFSRNoiseMaker(bits.params.idBits)
       bits.addr  := LFSRNoiseMaker(bits.params.addrBits)
       bits.len   := LFSRNoiseMaker(bits.params.lenBits)

src/main/scala/amba/axi4/Nodes.scala

@@ -16,7 +16,7 @@ object AXI4Imp extends SimpleNodeImp[AXI4MasterPortParameters, AXI4SlavePortPara
   def bundle(e: AXI4EdgeParameters) = AXI4Bundle(e.bundle)
   def render(e: AXI4EdgeParameters) = RenderedEdge(colour = "#00ccff" /* bluish */, label  = (e.slave.beatBytes * 8).toString)
 
-  override def monitor(bundle: AXI4Bundle, edge: AXI4EdgeParameters) {
+  override def monitor(bundle: AXI4Bundle, edge: AXI4EdgeParameters): Unit = {
     edge.params.lift(AXI4MonitorBuilder).foreach { builder =>
       val monitor = Module(builder(AXI4MonitorArgs(edge)))
       monitor.io.in := bundle

src/main/scala/amba/axi4/RegisterRouter.scala

@@ -133,5 +133,5 @@ trait HasAXI4ControlRegMap { this: RegisterRouter =>
   val controlXing: AXI4InwardCrossingHelper = this.crossIn(controlNode)
 
   // Internally, this function should be used to populate the control port with registers
-  protected def regmap(mapping: RegField.Map*) { controlNode.regmap(mapping:_*) }
+  protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
 }

src/main/scala/amba/axi4/Xbar.scala

@@ -235,7 +235,7 @@ object AXI4Xbar
 
 object AXI4Arbiter
 {
-  def apply[T <: Data](policy: TLArbiter.Policy)(sink: IrrevocableIO[T], sources: IrrevocableIO[T]*) {
+  def apply[T <: Data](policy: TLArbiter.Policy)(sink: IrrevocableIO[T], sources: IrrevocableIO[T]*): Unit = {
     if (sources.isEmpty) {
       sink.valid := Bool(false)
     } else {

src/main/scala/amba/axis/Bundles.scala

@@ -20,7 +20,7 @@ case class AXISKeepField(width: Int) extends SimpleBundleField(AXISKeep)(Output(
 case class AXISStrbField(width: Int) extends SimpleBundleField(AXISStrb)(Output(UInt(width.W)), ~0.U(width.W))
 case class AXISDataField(width: Int) extends BundleField(AXISData) {
   def data = Output(UInt(width.W))
-  def default(x: UInt) { x := DontCare }
+  def default(x: UInt): Unit = { x := DontCare }
 }
 
 class AXISBundleBits(val params: AXISBundleParameters) extends BundleMap(AXISBundle.keys(params)) {

src/main/scala/amba/axis/Xbar.scala

@@ -72,7 +72,7 @@ object AXISXbar
   def mapInputIds (ports: Seq[AXISMasterPortParameters]) = TLXbar.assignRanges(ports.map(_.endSourceId))
   def mapOutputIds(ports: Seq[AXISSlavePortParameters]) = TLXbar.assignRanges(ports.map(_.endDestinationId))
 
-  def arbitrate(policy: TLArbiter.Policy)(sink: AXISBundle, sources: Seq[AXISBundle]) {
+  def arbitrate(policy: TLArbiter.Policy)(sink: AXISBundle, sources: Seq[AXISBundle]): Unit = {
     if (sources.isEmpty) {
       sink.valid := false.B
     } else if (sources.size == 1) {

src/main/scala/amba/package.scala

@@ -19,7 +19,7 @@ package object amba {
   case object AMBAProt extends ControlKey[AMBAProtBundle]("amba_prot")
   case class AMBAProtField() extends BundleField(AMBAProt) {
     def data = Output(new AMBAProtBundle)
-    def default(x: AMBAProtBundle) {
+    def default(x: AMBAProtBundle): Unit = {
       x.bufferable := false.B
       x.modifiable := false.B
       x.readalloc  := false.B
@@ -34,6 +34,6 @@ package object amba {
   case object AMBACorrupt extends DataKey[Bool]("corrupt")
   case class AMBACorruptField() extends BundleField(AMBACorrupt) {
     def data = Output(Bool())
-    def default(x: Bool) { x := false.B }
+    def default(x: Bool): Unit = { x := false.B }
   }
 }

src/main/scala/diplomacy/FixedClockResource.scala

@@ -13,7 +13,7 @@ class FixedClockResource(val name: String, val freqMHz: Double, val prefix: Stri
         "compatible"         -> Seq(ResourceString("fixed-clock"))))
   }
 
-  def bind(dev: Device) {
+  def bind(dev: Device): Unit = {
     ResourceBinding { Resource(dev, "clocks").bind(ResourceReference(device.label)) }
   }
 }

src/main/scala/diplomacy/LazyModule.scala

@@ -141,7 +141,7 @@ abstract class LazyModule()(implicit val p: Parameters) {
     * @param buf String buffer to write to.
     * @param pad Padding as prefix for indentation purposes.
     */
-  private def nodesGraphML(buf: StringBuilder, pad: String) {
+  private def nodesGraphML(buf: StringBuilder, pad: String): Unit = {
     buf ++= s"""$pad<node id=\"$index\">\n"""
     buf ++= s"""$pad  <data key=\"n\"><y:ShapeNode><y:NodeLabel modelName=\"sides\" modelPosition=\"w\" rotationAngle=\"270.0\">$instanceName</y:NodeLabel><y:BorderStyle type=\"${if (shouldBeInlined) "dotted" else "line"}\"/></y:ShapeNode></data>\n"""
     buf ++= s"""$pad  <data key=\"d\">$moduleName ($pathName)</data>\n"""
@@ -162,7 +162,7 @@ abstract class LazyModule()(implicit val p: Parameters) {
     * @param buf String buffer to write to.
     * @param pad Padding as prefix for indentation purposes.
     */
-  private def edgesGraphML(buf: StringBuilder, pad: String) {
+  private def edgesGraphML(buf: StringBuilder, pad: String): Unit = {
     nodes.filter(!_.omitGraphML) foreach { n =>
       n.outputs.filter(!_._1.omitGraphML).foreach { case (o, edge) =>
         val RenderedEdge(colour, label, flipped) = edge
@@ -328,7 +328,7 @@ sealed trait LazyModuleImpLike extends RawModule {
     * Ask each [[BaseNode]] in [[wrapper.nodes]] to call [[BaseNode.finishInstantiate]].
     * Annotate this module to tell FIRRTL if it should be inlined.
     */
-  protected[diplomacy] def finishInstantiate() {
+  protected[diplomacy] def finishInstantiate(): Unit = {
     wrapper.nodes.reverse.foreach {
       _.finishInstantiate()
     }
@@ -538,7 +538,7 @@ object InModuleBody {
     val out = new ModuleValue[T] {
       var result: Option[T] = None
 
-      def execute() {
+      def execute(): Unit = {
         result = Some(body)
       }
 

src/main/scala/diplomacy/Nodes.scala

@@ -639,7 +639,7 @@ trait InwardNode[DI, UI, BI <: Data] extends BaseNode {
     * @param node    the [[OutwardNode]] to bind to this [[InwardNode]].
     * @param binding [[NodeBinding]] type.
     */
-  protected[diplomacy] def iPush(index: Int, node: OutwardNode[DI, UI, BI], binding: NodeBinding)(implicit p: Parameters, sourceInfo: SourceInfo) {
+  protected[diplomacy] def iPush(index: Int, node: OutwardNode[DI, UI, BI], binding: NodeBinding)(implicit p: Parameters, sourceInfo: SourceInfo): Unit = {
     val info = sourceLine(sourceInfo, " at ", "")
     require (!iRealized,
       s"""Diplomacy has detected a problem in your code:
@@ -732,7 +732,7 @@ trait OutwardNode[DO, UO, BO <: Data] extends BaseNode {
     * @param node    [[InwardNode]] to bind to.
     * @param binding Binding type.
     */
-  protected[diplomacy] def oPush(index: Int, node: InwardNode [DO, UO, BO], binding: NodeBinding)(implicit p: Parameters, sourceInfo: SourceInfo) {
+  protected[diplomacy] def oPush(index: Int, node: InwardNode [DO, UO, BO], binding: NodeBinding)(implicit p: Parameters, sourceInfo: SourceInfo): Unit = {
     val info = sourceLine(sourceInfo, " at ", "")
     require (!oRealized,
       s"""Diplomacy has detected a problem in your code:
@@ -1277,7 +1277,7 @@ sealed abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
   }
 
   /** Connects the outward part of a node with the inward part of this node. */
-  protected[diplomacy] def bind(h: OutwardNode[DI, UI, BI], binding: NodeBinding)(implicit p: Parameters, sourceInfo: SourceInfo) {
+  protected[diplomacy] def bind(h: OutwardNode[DI, UI, BI], binding: NodeBinding)(implicit p: Parameters, sourceInfo: SourceInfo): Unit = {
     val x = this // x := y
     val y = h
     val info = sourceLine(sourceInfo, " at ", "")

src/main/scala/diplomacy/Resources.scala

@@ -90,7 +90,7 @@ abstract class DeviceSnippet extends Device
 object Device
 {
   private var index: Int = 0
-  def skipIndexes(x: Int) { index += x }
+  def skipIndexes(x: Int): Unit = { index += x }
 }
 
 /** A trait for devices that generate interrupts. */
@@ -257,11 +257,11 @@ class MemoryDevice extends Device with DeviceRegName
 
 case class Resource(owner: Device, key: String)
 {
-  def bind(user: Device, value: ResourceValue) {
+  def bind(user: Device, value: ResourceValue): Unit = {
     val scope = BindingScope.active.get
     scope.resourceBindings = (this, Some(user), value) +: scope.resourceBindings
   }
-  def bind(value: ResourceValue) {
+  def bind(value: ResourceValue): Unit = {
     val scope = BindingScope.active.get
     scope.resourceBindings = (this, None, value) +: scope.resourceBindings
   }
@@ -403,7 +403,7 @@ object ResourceBinding
   /** Add a resource callback function to the callback list BindingScope.resourceBindingFns.
     * @param block      the callback function to be added.
     */
-  def apply(block: => Unit) {
+  def apply(block: => Unit): Unit = {
     val scope = BindingScope.find()
     require (scope.isDefined, "ResourceBinding must be called from within a BindingScope")
     scope.get.resourceBindingFns = { () => block } +: scope.get.resourceBindingFns

src/main/scala/formal/FormalUtils.scala

@@ -130,7 +130,7 @@ object SourceGet {
 object ResetUtils {
   def inactive_output_override[T <: Data](inactive_length: Int)
                                          (sigs: T,
-                                          override_assn: (T)=>Unit) {
+                                          override_assn: (T)=>Unit): Unit = {
     require(inactive_length >= 0)
 
     if(inactive_length>0) {

src/main/scala/jtag/JtagShifter.scala

@@ -21,7 +21,7 @@ class ShifterIO extends Bundle {
 
   /** Sets a output shifter IO's control signals from a input shifter IO's control signals.
     */
-  def chainControlFrom(in: ShifterIO) {
+  def chainControlFrom(in: ShifterIO): Unit = {
     shift := in.shift
     capture := in.capture
     update := in.update

src/main/scala/jtag/JtagTap.scala

@@ -244,7 +244,7 @@ object JtagTapGenerator {
       controllerInternal.io.dataChainIn := bypassChain.io.chainOut
     }
 
-    def mapInSelect(x: (Chain, Bool)) {
+    def mapInSelect(x: (Chain, Bool)): Unit = {
       val (chain, select) = x
       when (select) {
         chain.io.chainIn := controllerInternal.io.dataChainOut

src/main/scala/rocket/Events.scala

@@ -14,11 +14,11 @@ class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bo
     hits := events.map(_._2())
     gate(mask, hits.asUInt)
   }
-  def dump() {
+  def dump(): Unit = {
     for (((name, _), i) <- events.zipWithIndex)
       when (check(1.U << i)) { printf(s"Event $name\n") }
   }
-  def withCovers {
+  def withCovers: Unit = {
     events.zipWithIndex.foreach {
       case ((name, func), i) => cover(gate((1.U << i), (func() << i)), name)
     }
@@ -71,7 +71,7 @@ class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UI
 
   def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head))
 
-  def cover() { eventSets.foreach(_._1.foreach(_.withCovers)) }
+  def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) }
 
   private def decode(counter: UInt): (UInt, UInt) = {
     require(eventSets.size <= (1 << maxEventSetIdBits))

src/main/scala/rocket/PMP.scala

@@ -35,7 +35,7 @@ class PMPReg(implicit p: Parameters) extends CoreBundle()(p) {
   val cfg = new PMPConfig
   val addr = UInt((paddrBits - PMP.lgAlign).W)
 
-  def reset() {
+  def reset(): Unit = {
     cfg.a := 0
     cfg.l := 0
   }

src/main/scala/rocket/TLB.scala

@@ -114,7 +114,7 @@ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boo
     }
   }
 
-  def insert(tag: UInt, level: UInt, entry: TLBEntryData) {
+  def insert(tag: UInt, level: UInt, entry: TLBEntryData): Unit = {
     this.tag := tag
     this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0)
 
@@ -123,8 +123,8 @@ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boo
     data(idx) := entry.asUInt
   }
 
-  def invalidate() { valid.foreach(_ := false) }
-  def invalidateVPN(vpn: UInt) {
+  def invalidate(): Unit = { valid.foreach(_ := false) }
+  def invalidateVPN(vpn: UInt): Unit = {
     if (superpage) {
       when (hit(vpn)) { invalidate() }
     } else {
@@ -138,7 +138,7 @@ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boo
       }
     }
   }
-  def invalidateNonGlobal() {
+  def invalidateNonGlobal(): Unit = {
     for ((v, e) <- valid zip entry_data)
       when (!e.g) { v := false }
   }

src/main/scala/subsystem/InterruptBus.scala

@@ -61,7 +61,7 @@ trait HasSyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem =>
 trait HasExtInterruptsBundle {
   val interrupts: UInt
 
-  def tieOffInterrupts(dummy: Int = 1) {
+  def tieOffInterrupts(dummy: Int = 1): Unit = {
     interrupts := UInt(0)
   }
 }

src/main/scala/system/RocketTestSuite.scala

@@ -57,9 +57,9 @@ class RegressionTestSuite(val names: LinkedHashSet[String]) extends RocketTestSu
 object TestGeneration {
   private val suites = collection.mutable.ListMap[String, RocketTestSuite]()
 
-  def addSuite(s: RocketTestSuite) { suites += (s.makeTargetName -> s) }
+  def addSuite(s: RocketTestSuite): Unit = { suites += (s.makeTargetName -> s) }
 
-  def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
+  def addSuites(s: Seq[RocketTestSuite]): Unit = { s.foreach(addSuite) }
 
   private[rocketchip] def gen(kind: String, s: Seq[RocketTestSuite]) = {
     if(s.length > 0) {

src/main/scala/tile/BaseTile.scala

@@ -288,14 +288,14 @@ abstract class BaseTile private (val crossing: ClockCrossingType, q: Parameters)
   def rawReset = externalClockSinkNode.in.head._1.reset
 
   /** Helper function for connecting MMIO devices inside the tile to an xbar that will make them visible to external masters. */
-  def connectTLSlave(xbarNode: TLOutwardNode, node: TLNode, bytes: Int) {
+  def connectTLSlave(xbarNode: TLOutwardNode, node: TLNode, bytes: Int): Unit = {
     DisableMonitors { implicit p =>
       (Seq(node, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls))
         ++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
         .foldRight(xbarNode)(_ :*= _)
     }
   }
-  def connectTLSlave(node: TLNode, bytes: Int) { connectTLSlave(tlSlaveXbar.node, node, bytes) }
+  def connectTLSlave(node: TLNode, bytes: Int): Unit = { connectTLSlave(tlSlaveXbar.node, node, bytes) }
 
   /** TileLink node which represents the view that the intra-tile masters have of the rest of the system. */
   val visibilityNode = p(TileVisibilityNodeKey)