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Fix regression introduced by 79dd73a38c4b6ba8f2261b1f24bd6fa7094b1316 #2714

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merged 1 commit into from
Nov 10, 2020
+2 −2
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Fix regression introduced by 79dd73a38c4b6ba8f2261b1f24bd6fa7094b1316 #2714

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4 changes: 2 additions & 2 deletions src/main/scala/rocket/DCache.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -573,7 +573,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
tl_out_a.valid := !io.cpu.s2_kill &&
(s2_valid_uncached_pending ||
(s2_valid_cached_miss &&
!(release_ack_wait && release_ack_dirty) &&
!release_ack_wait &&
(cacheParams.acquireBeforeRelease && release_queue_empty || cacheParams.silentDrop && !s2_victim_dirty)))
tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param),
Mux(!s2_write, get,
Expand Down Expand Up @@ -858,7 +858,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
when (releaseDone) { release_state := s_voluntary_write_meta }
when (tl_out_c.fire() && c_first) {
release_ack_wait := true
release_ack_dirty := release_state === s_voluntary_release
release_ack_dirty := inWriteback
release_ack_addr := probe_bits.address
}
}
Expand Down