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Merge commit '577994e38' into create-targetDirKey #2767

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Merge commit '577994e38' into create-targetDirKey #2767

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11 changes: 8 additions & 3 deletions src/main/scala/stage/phases/PreElaboration.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -6,12 +6,14 @@ import chisel3.RawModule
import chisel3.stage.ChiselGeneratorAnnotation
import firrtl.AnnotationSeq
import firrtl.options.Viewer.view
import firrtl.options.{Dependency, Phase, PreservesAll}
import freechips.rocketchip.config.Parameters
import firrtl.options.{Dependency, Phase, PreservesAll, StageOptions}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.stage.RocketChipOptions
import freechips.rocketchip.util.HasRocketChipStageUtils

case object TargetDirKey extends Field[String](".")

/** Constructs a generator function that returns a top module with given config parameters */
class PreElaboration extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {

Expand All @@ -20,10 +22,13 @@ class PreElaboration extends Phase with PreservesAll[Phase] with HasRocketChipSt

override def transform(annotations: AnnotationSeq): AnnotationSeq = {

val stageOpts = view[StageOptions](annotations)
val rOpts = view[RocketChipOptions](annotations)
val topMod = rOpts.topModule.get

val config = getConfig(rOpts.configNames.get)
val config = getConfig(rOpts.configNames.get).alterPartial {
case TargetDirKey => stageOpts.targetDir
}

val gen = () =>
topMod
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