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PTW: timing L2TLB valid select write way #2868

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Aug 19, 2021
Merged

PTW: timing L2TLB valid select write way #2868

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PTW: timing L2TLB valid select write way
ingallsj Aug 18, 2021
c6a81fb
Reg:=Wire instead of Wire:=Reg
ingallsj Aug 18, 2021
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8 changes: 6 additions & 2 deletions src/main/scala/rocket/PTW.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -224,12 +224,16 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
val valid = RegInit(Vec(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W))))
val (r_tag, r_idx) = Split(r_req.addr, idxBits)
val r_valid_vec = valid.map(_(r_idx)).asUInt
val r_valid_vec_q = Wire(UInt(coreParams.nL2TLBWays.W))
val r_l2_plru_way = Wire(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W))
r_valid_vec_q := RegNext(r_valid_vec)
r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) RegNext(l2_plru.way(r_idx)) else 0.U)
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when (l2_refill && !invalidated) {
val entry = Wire(new L2TLBEntry(nL2TLBSets))
val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec.andR, UIntToOH(RegNext(l2_plru.way(r_idx)), coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec)) else 1.U(1.W)

entry := r_pte
entry.tag := r_tag

val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W)
ram.write(r_idx, Vec(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools)

val mask = UIntToOH(r_idx)
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