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refactor ReorderQueue to chisel3. #3094

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merged 1 commit into from
Oct 8, 2022
Merged

refactor ReorderQueue to chisel3. #3094

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33 changes: 17 additions & 16 deletions src/main/scala/util/ReorderQueue.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -3,11 +3,12 @@

package freechips.rocketchip.util

import Chisel._
import chisel3._
import chisel3.util.{DecoupledIO, Mux1H, OHToUInt, PriorityEncoder, PriorityEncoderOH}

class ReorderQueueWrite[T <: Data](dType: T, tagWidth: Int) extends Bundle {
val data = dType.cloneType
val tag = UInt(width = tagWidth)
val tag = UInt(tagWidth.W)

}

Expand All @@ -17,27 +18,27 @@ class ReorderEnqueueIO[T <: Data](dType: T, tagWidth: Int)
}

class ReorderDequeueIO[T <: Data](dType: T, tagWidth: Int) extends Bundle {
val valid = Bool(INPUT)
val tag = UInt(INPUT, tagWidth)
val data = dType.cloneType.asOutput
val matches = Bool(OUTPUT)
val valid = Input(Bool())
val tag = Input(UInt(tagWidth.W))
val data = Output(dType.cloneType)
val matches = Output(Bool())

}

class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Option[Int] = None)
extends Module {
val io = new Bundle {
val enq = new ReorderEnqueueIO(dType, tagWidth).flip
val io = IO(new Bundle {
val enq = Flipped(new ReorderEnqueueIO(dType, tagWidth))
val deq = new ReorderDequeueIO(dType, tagWidth)
}
})

val tagSpaceSize = 1 << tagWidth
val actualSize = size.getOrElse(tagSpaceSize)

if (tagSpaceSize > actualSize) {
val roq_data = Reg(Vec(actualSize, dType))
val roq_tags = Reg(Vec(actualSize, UInt(width = tagWidth)))
val roq_free = Reg(init = Vec.fill(actualSize)(Bool(true)))
val roq_tags = Reg(Vec(actualSize, UInt(tagWidth.W)))
val roq_free = RegInit(VecInit(Seq.fill(actualSize)(true.B)))

val roq_enq_addr = PriorityEncoder(roq_free)
val roq_matches = roq_tags.zip(roq_free)
Expand All @@ -51,29 +52,29 @@ class ReorderQueue[T <: Data](dType: T, tagWidth: Int, size: Option[Int] = None)
when (io.enq.valid && io.enq.ready) {
roq_data(roq_enq_addr) := io.enq.bits.data
roq_tags(roq_enq_addr) := io.enq.bits.tag
roq_free(roq_enq_addr) := Bool(false)
roq_free(roq_enq_addr) := false.B
}

when (io.deq.valid) {
roq_free(OHToUInt(roq_deq_onehot)) := Bool(true)
roq_free(OHToUInt(roq_deq_onehot)) := true.B
}

println(s"Warning - using a CAM for ReorderQueue, tagBits: ${tagWidth} size: ${actualSize}")
} else {
val roq_data = Mem(tagSpaceSize, dType)
val roq_free = Reg(init = Vec.fill(tagSpaceSize)(Bool(true)))
val roq_free = RegInit(VecInit(Seq.fill(tagSpaceSize)(true.B)))

io.enq.ready := roq_free(io.enq.bits.tag)
io.deq.data := roq_data(io.deq.tag)
io.deq.matches := !roq_free(io.deq.tag)

when (io.enq.valid && io.enq.ready) {
roq_data(io.enq.bits.tag) := io.enq.bits.data
roq_free(io.enq.bits.tag) := Bool(false)
roq_free(io.enq.bits.tag) := false.B
}

when (io.deq.valid) {
roq_free(io.deq.tag) := Bool(true)
roq_free(io.deq.tag) := true.B
}
}
}
Expand Down