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Error on unreliable name generation in VIO blackbox
Fixes #2497
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module DuplicateInputNames where | ||
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import Clash.Prelude | ||
import Clash.Cores.Xilinx.VIO | ||
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type Dom = XilinxSystem | ||
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inNames = "a" :> "a" :> Nil | ||
outNames = "b" :> Nil | ||
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topEntity :: | ||
"clk" ::: Clock Dom -> | ||
"in" ::: Signal Dom (Bit, Bit) -> | ||
"out" ::: Signal Dom Bit | ||
topEntity = vioProbe @Dom inNames outNames 0 |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,15 @@ | ||
module DuplicateInputOutputNames where | ||
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import Clash.Prelude | ||
import Clash.Cores.Xilinx.VIO | ||
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type Dom = XilinxSystem | ||
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inNames = "a" :> Nil | ||
outNames = "a" :> Nil | ||
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topEntity :: | ||
"clk" ::: Clock Dom -> | ||
"in" ::: Signal Dom Bit -> | ||
"out" ::: Signal Dom Bit | ||
topEntity = vioProbe @Dom inNames outNames 0 |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,14 @@ | ||
module DuplicateOutputNames where | ||
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import Clash.Prelude | ||
import Clash.Cores.Xilinx.VIO | ||
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type Dom = XilinxSystem | ||
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inNames = Nil | ||
outNames = "a" :> "a" :> Nil | ||
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topEntity :: | ||
"clk" ::: Clock Dom -> | ||
"out" ::: Signal Dom (Bit, Bit) | ||
topEntity = vioProbe @Dom inNames outNames (0, 0) |