Fix SPI xfer logic to use correct edge and timing #5
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This reads the SPI data while the clk is HIGH instead of low, and replaces the unecessary spin-loop with a single nop, resulting in a read frequency of ~1.4 MHz (measured via logic analyzer). Most SPI rams support reads up to at least 5 MHz. As a side effect, this significantly speeds up the flashing process, i.e. now it only takes 1.8s to flash the FPGA. This could be improved even more by getting rid of all the redundant spi_begin() and spi_end() calls, but at this point the flashing time is barely noticeable. pi@fpga:~/git/icotools/examples/icezero $ time ./icezprog ~/Downloads/default_te/python/gpio32_pwm6_te.bin Flash ID: EF 70 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Writing 0x000000 .. 0x00ffff: [erasing] [writing................] [readback................] Writing 0x010000 .. 0x01ffff: [erasing] [writing................] [readback................] Writing 0x020000 .. 0x02100a: [erasing] [writing..] [readback..] DONE. real 0m1.877s user 0m1.397s sys 0m0.261s
This way the FPGA can take over these lines, and start reading data from the SROM. Otherwise the reset might hang/fail.
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This fixes issue #3, and speeds up the flashing process. I've tested this on a vanilla Raspberry Pi Zero W.
pi@fpga:~/git/icotools/examples/icezero $ time ./icezprog ~/Downloads/default_te/python/gpio32_pwm6_te.bin
Flash ID: EF 70 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Writing 0x000000 .. 0x00ffff: [erasing] [writing................] [readback................]
Writing 0x010000 .. 0x01ffff: [erasing] [writing................] [readback................]
Writing 0x020000 .. 0x02100a: [erasing] [writing..] [readback..]
DONE.