rv64: implement instructions sets I, Zifenci, Zicsr, M, A, F, D, B

core-lang · Oct 14, 2023 · 148d41b · 148d41b
1 parent be7d129
commit 148d41b
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diff --git a/.cargo/config.toml b/.cargo/config.toml
@@ -0,0 +1,8 @@
+[build]
+target = "riscv64gc-unknown-linux-gnu"
+#
+#[target.aarch64-unknown-linux-gnu]
+#linker = "aarch64-linux-gnu-gcc"
+#
+[target.riscv64gc-unknown-linux-gnu]
+linker = "riscv64-linux-gnu-gcc"
diff --git a/dora-asm/src/lib.rs b/dora-asm/src/lib.rs
@@ -1,6 +1,7 @@
 use byteorder::{LittleEndian, WriteBytesExt};
 
 pub mod arm64;
+pub mod rv64;
 pub mod x64;
 
 use std::convert::TryInto;