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1. jcore-j1-ghdl jcore-j1-ghdl Public

   Forked from j-core/jcore-j1-ghdl

   A simple design targeting iCE40 up5k with GHDL + Yosys.

   VHDL 1

2. DFFRAM DFFRAM Public

   Forked from AUCOHL/DFFRAM

   Standard Cell Library based Memory Compiler using FF/Latch cells

   Verilog

3. OpenLane OpenLane Public

   Forked from The-OpenROAD-Project/OpenLane

   OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

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4. vhdl-svf vhdl-svf Public

   Forked from hansiglaser/vhdl-svf

   SVF (Serial Vector Format) interpreter to control a JTAG TAP

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5. minimal-lib minimal-lib Public

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6. openlane-vhdl-build openlane-vhdl-build Public

   Forked from j-core/openlane-vhdl-build

   Build scripts for tools to build j-core ASIC.

   Shell