ARM32: fix interface dispatch cell address transfer

[BredPet]

Signed-off-by: Petr Bred bredpetr@gmail.com

[BredPet]

wrong disasm:

movw    r12, #50152     ; 0xc3e8
movt    r12, #64        ; 0x40
ldr.w   r12, [r12]
ldr     r3, [r0, #0]
blx     r12

after fix:

movw    r12, #50136     ; 0xc3d8
movt    r12, #64        ; 0x40
ldr.w   r3, [r12]
ldr     r2, [r0, #0]
blx     r3

After this change we got a working version for ARM Tizen with RyuJIT and ILC/CoreRT compiler!!!
But only for a very simple example ;-)

[BredPet]

@Dmitri-Botcharnikov
@sergign60
@alpencolt
@jkotas please review

[jkotas]

Does the register need to be ever fixed for any platform? Should this rather be deleted?

[BredPet]

I'll try it on tests.

[BruceForstall]

What is the requirement here, for CoreRT?

I don't think deleting the line is correct. I thought that x64, at least, required the address in a specific register.

Does the change need to be specific to CoreRT and not change CoreCLR?

If you run diffs for x64, are there any?

[jkotas]

I have updated the CoreRT ABI doc in #14120 with CoreRT details.

I do not think any platform requires the target in a specific register. The only requirement is that the indirection that the target was fetched from has to be in a specific register. It is how it is written in https://github.com/dotnet/coreclr/blob/master/Documentation/botr/clr-abi.md at least.

My guess is that REG_JUMP_THUNK_PARAM is a left over from the legacy register allocator that was not able to get the target register scheduled and the target register value had to be hardcoded.

If there is a worry about regressing x64, I think we can keep the change under ifdef - but it may be nice to add a TODO comment that it is probably unnecessary.

[BruceForstall]

Would it be obvious, if looking at the VM stub code, whether it uses the stub address as currently set up (for amd64, e.g.)?

[jkotas]

There are 3 different stubs that this can go to. All of them trash RAX (ie REG_JUMP_THUNK_PARAM) almost immediately.

https://github.com/dotnet/coreclr/blob/master/src/vm/amd64/virtualcallstubcpu.hpp#L75
https://github.com/dotnet/coreclr/blob/master/src/vm/amd64/virtualcallstubcpu.hpp#L252
https://github.com/dotnet/coreclr/blob/master/src/vm/amd64/virtualcallstubcpu.hpp#L366

[BredPet]

@jkotas please review again

[BredPet]

@dotnet-bot test Tizen armel Cross Debug Build please

[jkotas]

@BruceForstall ?

[BruceForstall]

@dotnet-bot test Windows_NT arm Cross Checked Build and Test
@dotnet-bot test Windows_NT armlb Cross Checked Build and Test

[BredPet]

@dotnet-bot test Windows_NT arm Cross Checked Build and Test please
@dotnet-bot test Windows_NT armlb Cross Checked Build and Test please

[BredPet]

@BruceForstall please review again