Expose various integer intrinsics for Avx512F, Avx512BW, and Avx512CD (…

…#85833)

* Expose AlignRight32 and AlignRight64 on Avx512F

* Expose RotateLeft and RotateRight for Avx512F

* Expose SumAbsoluteDifferencesInBlock32 for Avx512BW + DetectConflicts and LeadingZeroCOunt for Avx512DQ

* Exponse TernaryLogic for Avx512F

* Apply formatting patch

* Ensure side effects are preserved when optimizing certain intrinsic imports

* Ensure the instruction code has the SIMD prefix before trying to encode the register

* Ensure side effects have been accounted for before swapping operands

* Move the complex ternary logic simplification logic to import, since the JIT will never produce such nodes itself

* Ensure gtNewSimdUnOpNode(GT_NOT) uses an in range constant for TernaryLogic

* Remove a new assert added to AND_NOT, logging an issue instead

* Add a missing `break;` statement

* Ensure val1/2/3 are GenTree** so swapping works and add a comment explaining the TernaryLogic table

* Fix formatting of a comment

* Don't double encode the 'vvvv' bits for `emitOutputAM`

* Avoid an assert in gtNewSimdCreateBroadcastNode for TYP_LONG on 32-bit

* Ensure we use CHECK_SPILL_ALL

* Ensure mustExpand is handled for `RotateLeft(Vector###<long>)` on 32-bit

* Make sure all tests are actually running and handle the "maybe no jmp table fallback"

* Handle a couple test issues  and ensure we set the constant when normalizing ~B | C

* Ensure ValidateRemaining uses firstOp[i]

src/coreclr/jit/compiler.h

@@ -2734,6 +2734,16 @@ class Compiler
     GenTree* gtNewSimdSumNode(
         var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);
 
+#if defined(TARGET_XARCH)
+    GenTree* gtNewSimdTernaryLogicNode(var_types   type,
+                                       GenTree*    op1,
+                                       GenTree*    op2,
+                                       GenTree*    op3,
+                                       GenTree*    op4,
+                                       CorInfoType simdBaseJitType,
+                                       unsigned    simdSize);
+#endif // TARGET_XARCH
+
     GenTree* gtNewSimdUnOpNode(genTreeOps  op,
                                var_types   type,
                                GenTree*    op1,