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Add CPUID for AVX10v2
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@khushal1996
khushal1996 committed Nov 12, 2024
1 parent eee9fd3 commit 3a53e0c
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Showing 14 changed files with 242 additions and 8 deletions.
1 change: 1 addition & 0 deletions src/coreclr/inc/clrconfigvalues.h
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Original file line number Diff line number Diff line change
Expand Up @@ -773,6 +773,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512F_VL, W("EnableAVX512F
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512VBMI, W("EnableAVX512VBMI"), 1, "Allows AVX512VBMI+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512VBMI_VL, W("EnableAVX512VBMI_VL"), 1, "Allows AVX512VBMI_VL+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX10v1, W("EnableAVX10v1"), 1, "Allows AVX10v1+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX10v2, W("EnableAVX10v2"), 1, "Allows AVX10v2+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNI, W("EnableAVXVNNI"), 1, "Allows AVXVNNI+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI1, W("EnableBMI1"), 1, "Allows BMI1+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI2, W("EnableBMI2"), 1, "Allows BMI2+ hardware intrinsics to be disabled")
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78 changes: 78 additions & 0 deletions src/coreclr/inc/corinfoinstructionset.h
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Original file line number Diff line number Diff line change
Expand Up @@ -145,6 +145,7 @@ enum CORINFO_InstructionSet
InstructionSet_AVX512VBMI_VL=33,
InstructionSet_AVX10v1=34,
InstructionSet_AVX10v1_V512=35,
<<<<<<< HEAD
InstructionSet_VectorT128=36,
InstructionSet_VectorT256=37,
InstructionSet_VectorT512=38,
Expand Down Expand Up @@ -175,6 +176,47 @@ enum CORINFO_InstructionSet
InstructionSet_AVX512VBMI_X64=63,
InstructionSet_AVX10v1_X64=64,
InstructionSet_AVX10v1_V512_X64=65,
=======
InstructionSet_AVX10v2=36,
InstructionSet_AVX10v2_V512=37,
InstructionSet_VectorT128=38,
InstructionSet_VectorT256=39,
InstructionSet_VectorT512=40,
InstructionSet_X86Base_X64=41,
InstructionSet_SSE_X64=42,
InstructionSet_SSE2_X64=43,
InstructionSet_SSE3_X64=44,
InstructionSet_SSSE3_X64=45,
InstructionSet_SSE41_X64=46,
InstructionSet_SSE42_X64=47,
InstructionSet_AVX_X64=48,
InstructionSet_AVX2_X64=49,
InstructionSet_AES_X64=50,
InstructionSet_BMI1_X64=51,
InstructionSet_BMI2_X64=52,
InstructionSet_FMA_X64=53,
InstructionSet_LZCNT_X64=54,
InstructionSet_PCLMULQDQ_X64=55,
InstructionSet_POPCNT_X64=56,
InstructionSet_AVXVNNI_X64=57,
InstructionSet_MOVBE_X64=58,
InstructionSet_X86Serialize_X64=59,
InstructionSet_EVEX_X64=60,
InstructionSet_AVX512F_X64=61,
InstructionSet_AVX512F_VL_X64=62,
InstructionSet_AVX512BW_X64=63,
InstructionSet_AVX512BW_VL_X64=64,
InstructionSet_AVX512CD_X64=65,
InstructionSet_AVX512CD_VL_X64=66,
InstructionSet_AVX512DQ_X64=67,
InstructionSet_AVX512DQ_VL_X64=68,
InstructionSet_AVX512VBMI_X64=69,
InstructionSet_AVX512VBMI_VL_X64=70,
InstructionSet_AVX10v1_X64=71,
InstructionSet_AVX10v1_V512_X64=72,
InstructionSet_AVX10v2_X64=73,
InstructionSet_AVX10v2_V512_X64=74,
>>>>>>> a55717e80fd (Add CPUID for AVX10v2)
#endif // TARGET_X86

};
Expand Down Expand Up @@ -344,6 +386,10 @@ struct CORINFO_InstructionSetFlags
AddInstructionSet(InstructionSet_AVX10v1_X64);
if (HasInstructionSet(InstructionSet_AVX10v1_V512))
AddInstructionSet(InstructionSet_AVX10v1_V512_X64);
if (HasInstructionSet(InstructionSet_AVX10v2))
AddInstructionSet(InstructionSet_AVX10v2_X64);
if (HasInstructionSet(InstructionSet_AVX10v2_V512))
AddInstructionSet(InstructionSet_AVX10v2_V512_X64);
#endif // TARGET_AMD64
#ifdef TARGET_X86
#endif // TARGET_X86
Expand Down Expand Up @@ -532,6 +578,14 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512_X64);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2_X64))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_X64);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512_X64))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512_X64);
if (resultflags.HasInstructionSet(InstructionSet_SSE) && !resultflags.HasInstructionSet(InstructionSet_X86Base))
resultflags.RemoveInstructionSet(InstructionSet_SSE);
if (resultflags.HasInstructionSet(InstructionSet_SSE2) && !resultflags.HasInstructionSet(InstructionSet_SSE))
Expand Down Expand Up @@ -624,6 +678,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX512VBMI_VL))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE))
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX))
Expand Down Expand Up @@ -730,6 +788,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX512VBMI_VL))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE))
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX))
Expand Down Expand Up @@ -934,6 +996,14 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
return "AVX10v1_V512";
case InstructionSet_AVX10v1_V512_X64 :
return "AVX10v1_V512_X64";
case InstructionSet_AVX10v2 :
return "AVX10v2";
case InstructionSet_AVX10v2_X64 :
return "AVX10v2_X64";
case InstructionSet_AVX10v2_V512 :
return "AVX10v2_V512";
case InstructionSet_AVX10v2_V512_X64 :
return "AVX10v2_V512_X64";
case InstructionSet_VectorT128 :
return "VectorT128";
case InstructionSet_VectorT256 :
Expand Down Expand Up @@ -1012,6 +1082,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
return "AVX10v1";
case InstructionSet_AVX10v1_V512 :
return "AVX10v1_V512";
case InstructionSet_AVX10v2 :
return "AVX10v2";
case InstructionSet_AVX10v2_V512 :
return "AVX10v2_V512";
case InstructionSet_VectorT128 :
return "VectorT128";
case InstructionSet_VectorT256 :
Expand Down Expand Up @@ -1085,6 +1159,8 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
case READYTORUN_INSTRUCTION_Avx512Vbmi_VL: return InstructionSet_AVX512VBMI_VL;
case READYTORUN_INSTRUCTION_Avx10v1: return InstructionSet_AVX10v1;
case READYTORUN_INSTRUCTION_Avx10v1_V512: return InstructionSet_AVX10v1_V512;
case READYTORUN_INSTRUCTION_Avx10v2: return InstructionSet_AVX10v2;
case READYTORUN_INSTRUCTION_Avx10v2_V512: return InstructionSet_AVX10v2_V512;
case READYTORUN_INSTRUCTION_VectorT128: return InstructionSet_VectorT128;
case READYTORUN_INSTRUCTION_VectorT256: return InstructionSet_VectorT256;
case READYTORUN_INSTRUCTION_VectorT512: return InstructionSet_VectorT512;
Expand Down Expand Up @@ -1122,6 +1198,8 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
case READYTORUN_INSTRUCTION_Avx512Vbmi_VL: return InstructionSet_AVX512VBMI_VL;
case READYTORUN_INSTRUCTION_Avx10v1: return InstructionSet_AVX10v1;
case READYTORUN_INSTRUCTION_Avx10v1_V512: return InstructionSet_AVX10v1_V512;
case READYTORUN_INSTRUCTION_Avx10v2: return InstructionSet_AVX10v2;
case READYTORUN_INSTRUCTION_Avx10v2_V512: return InstructionSet_AVX10v2_V512;
case READYTORUN_INSTRUCTION_VectorT128: return InstructionSet_VectorT128;
case READYTORUN_INSTRUCTION_VectorT256: return InstructionSet_VectorT256;
case READYTORUN_INSTRUCTION_VectorT512: return InstructionSet_VectorT512;
Expand Down
10 changes: 5 additions & 5 deletions src/coreclr/inc/jiteeversionguid.h
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Expand Up @@ -43,11 +43,11 @@ typedef const GUID *LPCGUID;
#define GUID_DEFINED
#endif // !GUID_DEFINED

constexpr GUID JITEEVersionIdentifier = { /* 04021b93-e969-41ed-96cd-4c583673b9ab */
0x04021b93,
0xe969,
0x41ed,
{0x96, 0xcd, 0x4c, 0x58, 0x36, 0x73, 0xb9, 0xab}
constexpr GUID JITEEVersionIdentifier = { /* c75035da-c692-4ef8-b84e-fbb44fd0f246 */
0xc75035da,
0xc692,
0x4ef8,
{0xb8, 0x4e, 0xfb, 0xb4, 0x4f, 0xd0, 0xf2, 0x46}
};

//////////////////////////////////////////////////////////////////////////////////////////////////////////
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/inc/readytoruninstructionset.h
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Expand Up @@ -55,6 +55,8 @@ enum ReadyToRunInstructionSet
READYTORUN_INSTRUCTION_Avx10v1=44,
READYTORUN_INSTRUCTION_Avx10v1_V512=46,
READYTORUN_INSTRUCTION_EVEX=47,
READYTORUN_INSTRUCTION_Avx10v2=48,
READYTORUN_INSTRUCTION_Avx10v2_V512=49,

};

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4 changes: 4 additions & 0 deletions src/coreclr/jit/hwintrinsic.cpp
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Expand Up @@ -801,6 +801,8 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
{ FIRST_NI_AVX512VBMI_VL, LAST_NI_AVX512VBMI_VL },
{ FIRST_NI_AVX10v1, LAST_NI_AVX10v1 },
{ FIRST_NI_AVX10v1_V512, LAST_NI_AVX10v1_V512 },
{ NI_Illegal, NI_Illegal }, // AVX10v2
{ NI_Illegal, NI_Illegal }, // AVX10v2_V512
{ NI_Illegal, NI_Illegal }, // VectorT128
{ NI_Illegal, NI_Illegal }, // VectorT256
{ NI_Illegal, NI_Illegal }, // VectorT512
Expand Down Expand Up @@ -831,6 +833,8 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
{ NI_Illegal, NI_Illegal }, // AVX512VBMI_X64
{ FIRST_NI_AVX10v1_X64, LAST_NI_AVX10v1_X64 },
{ NI_Illegal, NI_Illegal }, // AVX10v1_V512_X64
{ NI_Illegal, NI_Illegal }, // AVX10v2_X64
{ NI_Illegal, NI_Illegal }, // AVX10v2_V512_X64
#elif defined (TARGET_ARM64)
{ FIRST_NI_ArmBase, LAST_NI_ArmBase },
{ FIRST_NI_AdvSimd, LAST_NI_AdvSimd },
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1 change: 1 addition & 0 deletions src/coreclr/jit/jitconfigvalues.h
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Expand Up @@ -400,6 +400,7 @@ RELEASE_CONFIG_INTEGER(EnableAVX512F_VL, W("EnableAVX512F_VL"),
RELEASE_CONFIG_INTEGER(EnableAVX512VBMI, W("EnableAVX512VBMI"), 1) // Allows AVX512VBMI+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVX512VBMI_VL, W("EnableAVX512VBMI_VL"), 1) // Allows AVX512VBMI_VL+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVX10v1, W("EnableAVX10v1"), 1) // Allows AVX10v1+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVX10v2, W("EnableAVX10v2"), 1) // Allows AVX10v2+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVXVNNI, W("EnableAVXVNNI"), 1) // Allows AVXVNNI+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableBMI1, W("EnableBMI1"), 1) // Allows BMI1+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableBMI2, W("EnableBMI2"), 1) // Allows BMI2+ hardware intrinsics to be disabled
Expand Down
9 changes: 9 additions & 0 deletions src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs
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Expand Up @@ -78,6 +78,7 @@ private static class XArchIntrinsicConstants
public const int Serialize = 0x20000;
public const int Avx10v1 = 0x40000;
public const int Evex = 0x80000;
public const int Avx10v2 = 0x100000;

public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags)
{
Expand Down Expand Up @@ -135,6 +136,10 @@ public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags)
builder.AddSupportedInstructionSet("avx10v1_v512");
if ((flags & Evex) != 0)
builder.AddSupportedInstructionSet("evex");
if ((flags & Avx10v2) != 0)
builder.AddSupportedInstructionSet("avx10v2");
if (((flags & Avx10v2) != 0) && ((flags & Avx512) != 0))
builder.AddSupportedInstructionSet("avx10v2_v512");
}

public static int FromInstructionSet(InstructionSet instructionSet)
Expand Down Expand Up @@ -199,6 +204,10 @@ public static int FromInstructionSet(InstructionSet instructionSet)
InstructionSet.X64_AVX10v1_V512_X64 => (Avx10v1 | Avx512),
InstructionSet.X64_EVEX => Evex,
InstructionSet.X64_EVEX_X64 => Evex,
InstructionSet.X64_AVX10v2 => Avx10v2,
InstructionSet.X64_AVX10v2_X64 => Avx10v2,
InstructionSet.X64_AVX10v2_V512 => (Avx10v2 | Avx512),
InstructionSet.X64_AVX10v2_V512_X64 => (Avx10v2 | Avx512),

// Baseline ISAs - they're always available
InstructionSet.X64_SSE => 0,
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs
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Expand Up @@ -58,6 +58,8 @@ public enum ReadyToRunInstructionSet
Avx10v1=44,
Avx10v1_V512=46,
EVEX=47,
Avx10v2=48,
Avx10v2_V512=49,

}
}
8 changes: 8 additions & 0 deletions src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs
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Expand Up @@ -119,6 +119,10 @@ public static class ReadyToRunInstructionSetHelper
case InstructionSet.X64_AVX10v1_X64: return ReadyToRunInstructionSet.Avx10v1;
case InstructionSet.X64_AVX10v1_V512: return ReadyToRunInstructionSet.Avx10v1_V512;
case InstructionSet.X64_AVX10v1_V512_X64: return ReadyToRunInstructionSet.Avx10v1_V512;
case InstructionSet.X64_AVX10v2: return ReadyToRunInstructionSet.Avx10v2;
case InstructionSet.X64_AVX10v2_X64: return ReadyToRunInstructionSet.Avx10v2;
case InstructionSet.X64_AVX10v2_V512: return ReadyToRunInstructionSet.Avx10v2_V512;
case InstructionSet.X64_AVX10v2_V512_X64: return ReadyToRunInstructionSet.Avx10v2_V512;
case InstructionSet.X64_VectorT128: return ReadyToRunInstructionSet.VectorT128;
case InstructionSet.X64_VectorT256: return ReadyToRunInstructionSet.VectorT256;
case InstructionSet.X64_VectorT512: return ReadyToRunInstructionSet.VectorT512;
Expand Down Expand Up @@ -193,6 +197,10 @@ public static class ReadyToRunInstructionSetHelper
case InstructionSet.X86_AVX10v1_X64: return null;
case InstructionSet.X86_AVX10v1_V512: return ReadyToRunInstructionSet.Avx10v1_V512;
case InstructionSet.X86_AVX10v1_V512_X64: return null;
case InstructionSet.X86_AVX10v2: return ReadyToRunInstructionSet.Avx10v2;
case InstructionSet.X86_AVX10v2_X64: return null;
case InstructionSet.X86_AVX10v2_V512: return ReadyToRunInstructionSet.Avx10v2_V512;
case InstructionSet.X86_AVX10v2_V512_X64: return null;
case InstructionSet.X86_VectorT128: return ReadyToRunInstructionSet.VectorT128;
case InstructionSet.X86_VectorT256: return ReadyToRunInstructionSet.VectorT256;
case InstructionSet.X86_VectorT512: return ReadyToRunInstructionSet.VectorT512;
Expand Down
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