Skip to content

Commit

Permalink
Adding CPUID for AVX10.2 (#109302)
Browse files Browse the repository at this point in the history 
* Add CPUID for AVX10.2

* Handle AVX10.2 ISAs in missing places

* Remove APX_X64 since it is unused

* remove log file and change handling for AVX10v2_V512

* resolve merge errors
  • Loading branch information
@khushal1996
khushal1996 authored Nov 21, 2024
1 parent 3b91ac6 commit 5345dc5
Show file tree
Hide file tree
Showing 17 changed files with 286 additions and 108 deletions.
1 change: 1 addition & 0 deletions src/coreclr/inc/clrconfigvalues.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -771,6 +771,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512F_VL, W("EnableAVX512F
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512VBMI, W("EnableAVX512VBMI"), 1, "Allows AVX512VBMI+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512VBMI_VL, W("EnableAVX512VBMI_VL"), 1, "Allows AVX512VBMI_VL+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX10v1, W("EnableAVX10v1"), 1, "Allows AVX10v1+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX10v2, W("EnableAVX10v2"), 1, "Allows AVX10v2+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNI, W("EnableAVXVNNI"), 1, "Allows AVXVNNI+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI1, W("EnableBMI1"), 1, "Allows BMI1+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI2, W("EnableBMI2"), 1, "Allows BMI2+ hardware intrinsics to be disabled")
Expand Down
144 changes: 94 additions & 50 deletions src/coreclr/inc/corinfoinstructionset.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -84,31 +84,35 @@ enum CORINFO_InstructionSet
InstructionSet_VectorT256=39,
InstructionSet_VectorT512=40,
InstructionSet_APX=41,
InstructionSet_X86Base_X64=42,
InstructionSet_SSE_X64=43,
InstructionSet_SSE2_X64=44,
InstructionSet_SSE3_X64=45,
InstructionSet_SSSE3_X64=46,
InstructionSet_SSE41_X64=47,
InstructionSet_SSE42_X64=48,
InstructionSet_AVX_X64=49,
InstructionSet_AVX2_X64=50,
InstructionSet_AES_X64=51,
InstructionSet_BMI1_X64=52,
InstructionSet_BMI2_X64=53,
InstructionSet_FMA_X64=54,
InstructionSet_LZCNT_X64=55,
InstructionSet_PCLMULQDQ_X64=56,
InstructionSet_POPCNT_X64=57,
InstructionSet_AVXVNNI_X64=58,
InstructionSet_X86Serialize_X64=59,
InstructionSet_AVX512F_X64=60,
InstructionSet_AVX512BW_X64=61,
InstructionSet_AVX512CD_X64=62,
InstructionSet_AVX512DQ_X64=63,
InstructionSet_AVX512VBMI_X64=64,
InstructionSet_AVX10v1_X64=65,
InstructionSet_AVX10v1_V512_X64=66,
InstructionSet_AVX10v2=42,
InstructionSet_AVX10v2_V512=43,
InstructionSet_X86Base_X64=44,
InstructionSet_SSE_X64=45,
InstructionSet_SSE2_X64=46,
InstructionSet_SSE3_X64=47,
InstructionSet_SSSE3_X64=48,
InstructionSet_SSE41_X64=49,
InstructionSet_SSE42_X64=50,
InstructionSet_AVX_X64=51,
InstructionSet_AVX2_X64=52,
InstructionSet_AES_X64=53,
InstructionSet_BMI1_X64=54,
InstructionSet_BMI2_X64=55,
InstructionSet_FMA_X64=56,
InstructionSet_LZCNT_X64=57,
InstructionSet_PCLMULQDQ_X64=58,
InstructionSet_POPCNT_X64=59,
InstructionSet_AVXVNNI_X64=60,
InstructionSet_X86Serialize_X64=61,
InstructionSet_AVX512F_X64=62,
InstructionSet_AVX512BW_X64=63,
InstructionSet_AVX512CD_X64=64,
InstructionSet_AVX512DQ_X64=65,
InstructionSet_AVX512VBMI_X64=66,
InstructionSet_AVX10v1_X64=67,
InstructionSet_AVX10v1_V512_X64=68,
InstructionSet_AVX10v2_X64=69,
InstructionSet_AVX10v2_V512_X64=70,
#endif // TARGET_AMD64
#ifdef TARGET_X86
InstructionSet_X86Base=1,
Expand Down Expand Up @@ -152,31 +156,35 @@ enum CORINFO_InstructionSet
InstructionSet_VectorT256=39,
InstructionSet_VectorT512=40,
InstructionSet_APX=41,
InstructionSet_X86Base_X64=42,
InstructionSet_SSE_X64=43,
InstructionSet_SSE2_X64=44,
InstructionSet_SSE3_X64=45,
InstructionSet_SSSE3_X64=46,
InstructionSet_SSE41_X64=47,
InstructionSet_SSE42_X64=48,
InstructionSet_AVX_X64=49,
InstructionSet_AVX2_X64=50,
InstructionSet_AES_X64=51,
InstructionSet_BMI1_X64=52,
InstructionSet_BMI2_X64=53,
InstructionSet_FMA_X64=54,
InstructionSet_LZCNT_X64=55,
InstructionSet_PCLMULQDQ_X64=56,
InstructionSet_POPCNT_X64=57,
InstructionSet_AVXVNNI_X64=58,
InstructionSet_X86Serialize_X64=59,
InstructionSet_AVX512F_X64=60,
InstructionSet_AVX512BW_X64=61,
InstructionSet_AVX512CD_X64=62,
InstructionSet_AVX512DQ_X64=63,
InstructionSet_AVX512VBMI_X64=64,
InstructionSet_AVX10v1_X64=65,
InstructionSet_AVX10v1_V512_X64=66,
InstructionSet_AVX10v2=42,
InstructionSet_AVX10v2_V512=43,
InstructionSet_X86Base_X64=44,
InstructionSet_SSE_X64=45,
InstructionSet_SSE2_X64=46,
InstructionSet_SSE3_X64=47,
InstructionSet_SSSE3_X64=48,
InstructionSet_SSE41_X64=49,
InstructionSet_SSE42_X64=50,
InstructionSet_AVX_X64=51,
InstructionSet_AVX2_X64=52,
InstructionSet_AES_X64=53,
InstructionSet_BMI1_X64=54,
InstructionSet_BMI2_X64=55,
InstructionSet_FMA_X64=56,
InstructionSet_LZCNT_X64=57,
InstructionSet_PCLMULQDQ_X64=58,
InstructionSet_POPCNT_X64=59,
InstructionSet_AVXVNNI_X64=60,
InstructionSet_X86Serialize_X64=61,
InstructionSet_AVX512F_X64=62,
InstructionSet_AVX512BW_X64=63,
InstructionSet_AVX512CD_X64=64,
InstructionSet_AVX512DQ_X64=65,
InstructionSet_AVX512VBMI_X64=66,
InstructionSet_AVX10v1_X64=67,
InstructionSet_AVX10v1_V512_X64=68,
InstructionSet_AVX10v2_X64=69,
InstructionSet_AVX10v2_V512_X64=70,
#endif // TARGET_X86

};
Expand Down Expand Up @@ -342,6 +350,10 @@ struct CORINFO_InstructionSetFlags
AddInstructionSet(InstructionSet_AVX10v1_X64);
if (HasInstructionSet(InstructionSet_AVX10v1_V512))
AddInstructionSet(InstructionSet_AVX10v1_V512_X64);
if (HasInstructionSet(InstructionSet_AVX10v2))
AddInstructionSet(InstructionSet_AVX10v2_X64);
if (HasInstructionSet(InstructionSet_AVX10v2_V512))
AddInstructionSet(InstructionSet_AVX10v2_V512_X64);
#endif // TARGET_AMD64
#ifdef TARGET_X86
#endif // TARGET_X86
Expand Down Expand Up @@ -522,6 +534,14 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512_X64);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2_X64))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_X64);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512_X64))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512_X64) && !resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512_X64);
if (resultflags.HasInstructionSet(InstructionSet_SSE) && !resultflags.HasInstructionSet(InstructionSet_X86Base))
resultflags.RemoveInstructionSet(InstructionSet_SSE);
if (resultflags.HasInstructionSet(InstructionSet_SSE2) && !resultflags.HasInstructionSet(InstructionSet_SSE))
Expand Down Expand Up @@ -622,6 +642,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX512VBMI_VL))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE))
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX))
Expand Down Expand Up @@ -736,6 +760,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX512VBMI_VL))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v1_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE))
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX))
Expand Down Expand Up @@ -948,6 +976,14 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
return "VectorT512";
case InstructionSet_APX :
return "APX";
case InstructionSet_AVX10v2 :
return "AVX10v2";
case InstructionSet_AVX10v2_X64 :
return "AVX10v2_X64";
case InstructionSet_AVX10v2_V512 :
return "AVX10v2_V512";
case InstructionSet_AVX10v2_V512_X64 :
return "AVX10v2_V512_X64";
#endif // TARGET_AMD64
#ifdef TARGET_X86
case InstructionSet_X86Base :
Expand Down Expand Up @@ -1032,6 +1068,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
return "VectorT512";
case InstructionSet_APX :
return "APX";
case InstructionSet_AVX10v2 :
return "AVX10v2";
case InstructionSet_AVX10v2_V512 :
return "AVX10v2_V512";
#endif // TARGET_X86

default:
Expand Down Expand Up @@ -1105,6 +1145,8 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
case READYTORUN_INSTRUCTION_VectorT256: return InstructionSet_VectorT256;
case READYTORUN_INSTRUCTION_VectorT512: return InstructionSet_VectorT512;
case READYTORUN_INSTRUCTION_Apx: return InstructionSet_APX;
case READYTORUN_INSTRUCTION_Avx10v2: return InstructionSet_AVX10v2;
case READYTORUN_INSTRUCTION_Avx10v2_V512: return InstructionSet_AVX10v2_V512;
#endif // TARGET_AMD64
#ifdef TARGET_X86
case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base;
Expand Down Expand Up @@ -1145,6 +1187,8 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
case READYTORUN_INSTRUCTION_VectorT256: return InstructionSet_VectorT256;
case READYTORUN_INSTRUCTION_VectorT512: return InstructionSet_VectorT512;
case READYTORUN_INSTRUCTION_Apx: return InstructionSet_APX;
case READYTORUN_INSTRUCTION_Avx10v2: return InstructionSet_AVX10v2;
case READYTORUN_INSTRUCTION_Avx10v2_V512: return InstructionSet_AVX10v2_V512;
#endif // TARGET_X86

default:
Expand Down
10 changes: 5 additions & 5 deletions src/coreclr/inc/jiteeversionguid.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,11 +43,11 @@ typedef const GUID *LPCGUID;
#define GUID_DEFINED
#endif // !GUID_DEFINED

constexpr GUID JITEEVersionIdentifier = { /* 9014d652-5dc7-4edf-9285-6644d0898fb5 */
0x9014d652,
0x5dc7,
0x4edf,
{0x92, 0x85, 0x66, 0x44, 0xd0, 0x89, 0x8f, 0xb5}
constexpr GUID JITEEVersionIdentifier = { /* 9ed85c09-d33d-4855-80ea-e3b7330e8173 */
0x9ed85c09,
0xd33d,
0x4855,
{0x80, 0xea, 0xe3, 0xb7, 0x33, 0x0e, 0x81, 0x73}
};

//////////////////////////////////////////////////////////////////////////////////////////////////////////
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/inc/readytoruninstructionset.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,8 @@ enum ReadyToRunInstructionSet
READYTORUN_INSTRUCTION_Apx=48,
READYTORUN_INSTRUCTION_Pclmulqdq_V256=49,
READYTORUN_INSTRUCTION_Pclmulqdq_V512=50,
READYTORUN_INSTRUCTION_Avx10v2=51,
READYTORUN_INSTRUCTION_Avx10v2_V512=52,

};

Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/jit/hwintrinsic.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -807,6 +807,8 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
{ NI_Illegal, NI_Illegal }, // VectorT256
{ NI_Illegal, NI_Illegal }, // VectorT512
{ NI_Illegal, NI_Illegal }, // APX
{ NI_Illegal, NI_Illegal }, // AVX10v2
{ NI_Illegal, NI_Illegal }, // AVX10v2_V512
{ FIRST_NI_X86Base_X64, LAST_NI_X86Base_X64 },
{ FIRST_NI_SSE_X64, LAST_NI_SSE_X64 },
{ FIRST_NI_SSE2_X64, LAST_NI_SSE2_X64 },
Expand All @@ -832,6 +834,8 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
{ NI_Illegal, NI_Illegal }, // AVX512VBMI_X64
{ FIRST_NI_AVX10v1_X64, LAST_NI_AVX10v1_X64 },
{ NI_Illegal, NI_Illegal }, // AVX10v1_V512_X64
{ NI_Illegal, NI_Illegal }, // AVX10v2_X64
{ NI_Illegal, NI_Illegal }, // AVX10v2_V512_X64
#elif defined (TARGET_ARM64)
{ FIRST_NI_ArmBase, LAST_NI_ArmBase },
{ FIRST_NI_AdvSimd, LAST_NI_AdvSimd },
Expand Down
1 change: 1 addition & 0 deletions src/coreclr/jit/jitconfigvalues.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -400,6 +400,7 @@ RELEASE_CONFIG_INTEGER(EnableAVX512F_VL, "EnableAVX512F_VL",
RELEASE_CONFIG_INTEGER(EnableAVX512VBMI, "EnableAVX512VBMI", 1) // Allows AVX512VBMI+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVX512VBMI_VL, "EnableAVX512VBMI_VL", 1) // Allows AVX512VBMI_VL+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVX10v1, "EnableAVX10v1", 1) // Allows AVX10v1+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVX10v2, "EnableAVX10v2", 1) // Allows AVX10v2+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVXVNNI, "EnableAVXVNNI", 1) // Allows AVXVNNI+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableBMI1, "EnableBMI1", 1) // Allows BMI1+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableBMI2, "EnableBMI2", 1) // Allows BMI2+ hardware intrinsics to be disabled
Expand Down
9 changes: 9 additions & 0 deletions src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,7 @@ private static class XArchIntrinsicConstants
public const int Evex = 0x80000;
public const int Apx = 0x100000;
public const int Vpclmulqdq = 0x200000;
public const int Avx10v2 = 0x400000;

public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags)
{
Expand Down Expand Up @@ -145,6 +146,10 @@ public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags)
if ((flags & Avx512) != 0)
builder.AddSupportedInstructionSet("vpclmul_v512");
}
if ((flags & Avx10v2) != 0)
builder.AddSupportedInstructionSet("avx10v2");
if (((flags & Avx10v2) != 0) && ((flags & Avx512) != 0))
builder.AddSupportedInstructionSet("avx10v2_v512");
}

public static int FromInstructionSet(InstructionSet instructionSet)
Expand Down Expand Up @@ -210,6 +215,10 @@ public static int FromInstructionSet(InstructionSet instructionSet)
InstructionSet.X64_APX => Apx,
InstructionSet.X64_PCLMULQDQ_V256 => Vpclmulqdq,
InstructionSet.X64_PCLMULQDQ_V512 => (Vpclmulqdq | Avx512),
InstructionSet.X64_AVX10v2 => Avx10v2,
InstructionSet.X64_AVX10v2_X64 => Avx10v2,
InstructionSet.X64_AVX10v2_V512 => (Avx10v2 | Avx512),
InstructionSet.X64_AVX10v2_V512_X64 => (Avx10v2 | Avx512),

// Baseline ISAs - they're always available
InstructionSet.X64_SSE => 0,
Expand Down
5 changes: 5 additions & 0 deletions src/coreclr/tools/Common/Compiler/InstructionSetSupport.cs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -360,6 +360,11 @@ public bool ComputeInstructionSetFlags(int maxVectorTBitWidth,

if (_supportedInstructionSets.Contains("vpclmul"))
_supportedInstructionSets.Add("vpclmul_v512");

// Having AVX10V2 and any AVX-512 instruction sets enabled,
// automatically implies AVX10V2-V512 as well.
if (_supportedInstructionSets.Contains("avx10v2"))
_supportedInstructionSets.Add("avx10v2_v512");
}

foreach (string supported in _supportedInstructionSets)
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/tools/Common/InstructionSetHelpers.cs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -228,6 +228,8 @@ public static InstructionSetSupport ConfigureInstructionSetSupport(string instru
optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avx10v1");
optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avx10v1_v512");
optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("vpclmul_v512");
optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avx10v2");
optimisticInstructionSetSupportBuilder.AddSupportedInstructionSet("avx10v2_v512");
}
}
else if (targetArchitecture == TargetArchitecture.ARM64)
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,8 @@ public enum ReadyToRunInstructionSet
Apx=48,
Pclmulqdq_V256=49,
Pclmulqdq_V512=50,
Avx10v2=51,
Avx10v2_V512=52,

}
}
8 changes: 8 additions & 0 deletions src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -123,6 +123,10 @@ public static class ReadyToRunInstructionSetHelper
case InstructionSet.X64_VectorT256: return ReadyToRunInstructionSet.VectorT256;
case InstructionSet.X64_VectorT512: return ReadyToRunInstructionSet.VectorT512;
case InstructionSet.X64_APX: return ReadyToRunInstructionSet.Apx;
case InstructionSet.X64_AVX10v2: return ReadyToRunInstructionSet.Avx10v2;
case InstructionSet.X64_AVX10v2_X64: return ReadyToRunInstructionSet.Avx10v2;
case InstructionSet.X64_AVX10v2_V512: return ReadyToRunInstructionSet.Avx10v2_V512;
case InstructionSet.X64_AVX10v2_V512_X64: return ReadyToRunInstructionSet.Avx10v2_V512;

default: throw new Exception("Unknown instruction set");
}
Expand Down Expand Up @@ -198,6 +202,10 @@ public static class ReadyToRunInstructionSetHelper
case InstructionSet.X86_VectorT256: return ReadyToRunInstructionSet.VectorT256;
case InstructionSet.X86_VectorT512: return ReadyToRunInstructionSet.VectorT512;
case InstructionSet.X86_APX: return ReadyToRunInstructionSet.Apx;
case InstructionSet.X86_AVX10v2: return ReadyToRunInstructionSet.Avx10v2;
case InstructionSet.X86_AVX10v2_X64: return null;
case InstructionSet.X86_AVX10v2_V512: return ReadyToRunInstructionSet.Avx10v2_V512;
case InstructionSet.X86_AVX10v2_V512_X64: return null;

default: throw new Exception("Unknown instruction set");
}
Expand Down
Loading

0 comments on commit 5345dc5

Please sign in to comment.