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[RISC-V] Add crossgen2 for riscv64 (#95188)
* Add crossgen2 for riscv64 * Fix review comments * Fix review
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32 changes: 32 additions & 0 deletions
32
src/coreclr/tools/Common/Compiler/DependencyAnalysis/Target_RiscV64/AddrMode.cs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,32 @@ | ||
| // Licensed to the .NET Foundation under one or more agreements. | ||
| // The .NET Foundation licenses this file to you under the MIT license. | ||
|
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| namespace ILCompiler.DependencyAnalysis.RiscV64 | ||
| { | ||
| public enum AddrModeSize | ||
| { | ||
| Int8 = 1, | ||
| Int16 = 2, | ||
| Int32 = 4, | ||
| Int64 = 8, | ||
| Int128 = 16 | ||
| } | ||
|
|
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| public struct AddrMode | ||
| { | ||
| public readonly Register BaseReg; | ||
| public readonly Register? IndexReg; | ||
| public readonly int Offset; | ||
| public readonly byte Scale; | ||
| public readonly AddrModeSize Size; | ||
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| public AddrMode(Register baseRegister, Register? indexRegister, int offset, byte scale, AddrModeSize size) | ||
| { | ||
| BaseReg = baseRegister; | ||
| IndexReg = indexRegister; | ||
| Offset = offset; | ||
| Scale = scale; | ||
| Size = size; | ||
| } | ||
| } | ||
| } |
44 changes: 44 additions & 0 deletions
44
src/coreclr/tools/Common/Compiler/DependencyAnalysis/Target_RiscV64/Register.cs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,44 @@ | ||
| // Licensed to the .NET Foundation under one or more agreements. | ||
| // The .NET Foundation licenses this file to you under the MIT license. | ||
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| namespace ILCompiler.DependencyAnalysis.RiscV64 | ||
| { | ||
| public enum Register | ||
| { | ||
| X0, | ||
| X1, | ||
| X2, | ||
| X3, | ||
| X4, | ||
| X5, | ||
| X6, | ||
| X7, | ||
| X8, | ||
| X9, | ||
| X10, | ||
| X11, | ||
| X12, | ||
| X13, | ||
| X14, | ||
| X15, | ||
| X16, | ||
| X17, | ||
| X18, | ||
| X19, | ||
| X20, | ||
| X21, | ||
| X22, | ||
| X23, | ||
| X24, | ||
| X25, | ||
| X26, | ||
| X27, | ||
| X28, | ||
| X29, | ||
| X30, | ||
| X31, | ||
|
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| None, | ||
| NoIndex = 128 | ||
| } | ||
| } |
135 changes: 135 additions & 0 deletions
135
src/coreclr/tools/Common/Compiler/DependencyAnalysis/Target_RiscV64/RiscV64Emitter.cs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,135 @@ | ||
| // Licensed to the .NET Foundation under one or more agreements. | ||
| // The .NET Foundation licenses this file to you under the MIT license. | ||
|
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| using System; | ||
| using System.Diagnostics; | ||
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| namespace ILCompiler.DependencyAnalysis.RiscV64 | ||
| { | ||
| public struct RiscV64Emitter | ||
| { | ||
| public RiscV64Emitter(NodeFactory factory, bool relocsOnly) | ||
| { | ||
| Builder = new ObjectDataBuilder(factory, relocsOnly); | ||
| TargetRegister = new TargetRegisterMap(factory.Target.OperatingSystem); | ||
| } | ||
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| public ObjectDataBuilder Builder; | ||
| public TargetRegisterMap TargetRegister; | ||
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| // Assembly stub creation api. TBD, actually make this general purpose | ||
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| //ebreak | ||
| public void EmitBreak() | ||
| { | ||
| Builder.EmitUInt(0x00100073); | ||
| } | ||
|
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| public void EmitLI(Register regDst, int offset) | ||
| { | ||
| Debug.Assert((offset >= -2048) && (offset <= 2047)); | ||
| EmitADDI(regDst, Register.X0, offset); | ||
| } | ||
|
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| public void EmitMOV(Register regDst, Register regSrc) | ||
| { | ||
| EmitADDI(regDst, regSrc, 0); | ||
| } | ||
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| public void EmitMOV(Register regDst, ISymbolNode symbol) | ||
| { | ||
| Builder.EmitReloc(symbol, RelocType.IMAGE_REL_BASED_RISCV64_PC); | ||
| //auipc reg, off-hi-20bits | ||
| EmitPC(regDst); | ||
| //addi reg, reg, off-lo-12bits | ||
| EmitADDI(regDst, regDst, 0); | ||
| } | ||
|
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| // auipc regDst, 0 | ||
| public void EmitPC(Register regDst) | ||
| { | ||
| Debug.Assert((uint)regDst > 0 && (uint)regDst < 32); | ||
| Builder.EmitUInt(0x00000017u | (uint)regDst << 7); | ||
| } | ||
|
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| // addi regDst, regSrc, offset | ||
| public void EmitADDI(Register regDst, Register regSrc, int offset) | ||
| { | ||
| Debug.Assert((uint)regDst <= 0x1f); | ||
| Debug.Assert((uint)regSrc <= 0x1f); | ||
| Debug.Assert((offset >= -2048) && (offset <= 2047)); | ||
| Builder.EmitUInt((uint)(0x00000013u | ((uint)regSrc << 15) | ((uint)regDst << 7) | (uint)((offset & 0xfff) << 20))); | ||
| } | ||
|
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| // xori regDst, regSrc, offset | ||
| public void EmitXORI(Register regDst, Register regSrc, int offset) | ||
| { | ||
| Debug.Assert((offset >= -2048) && (offset <= 2047)); | ||
| Builder.EmitUInt((uint)(0x00004013u | ((uint)regSrc << 15) | ((uint)regDst << 7) | (uint)((offset & 0xfff) << 20))); | ||
| } | ||
|
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| // ld regDst, offset(regSrc) | ||
| public void EmitLD(Register regDst, Register regSrc, int offset) | ||
| { | ||
| Debug.Assert((offset >= -2048) && (offset <= 2047)); | ||
| Builder.EmitUInt((uint)(0x00003003u | ((uint)regSrc << 15) | ((uint)regDst << 7) | (uint)((offset & 0xfff) << 20))); | ||
| } | ||
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| // jalr regDst, offset(regSrc) | ||
| public void EmitJALR(Register regDst, Register regSrc, int offset) | ||
| { | ||
| Debug.Assert((offset >= -2048) && (offset <= 2047)); | ||
| Builder.EmitUInt((uint)(0x00000067u | ((uint)regSrc << 15) | ((uint)regDst << 7) | (uint)((offset & 0xfff) << 20))); | ||
| } | ||
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| public void EmitRET() | ||
| { | ||
| // jalr x0,0(x1) | ||
| EmitJALR(Register.X0, Register.X1, 0); | ||
| } | ||
|
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| public void EmitJMP(Register reg) | ||
| { | ||
| //jalr x0, 0(reg) | ||
| EmitJALR(Register.X0, reg, 0); | ||
| } | ||
|
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| public void EmitJMP(ISymbolNode symbol) | ||
| { | ||
| if (symbol.RepresentsIndirectionCell) | ||
| { | ||
| //auipc x29, 0 | ||
| EmitPC(Register.X29); | ||
| //ld x29,16(x29) | ||
| EmitLD(Register.X29, Register.X29, 16); | ||
| //ld x29,0(x29) | ||
| EmitLD(Register.X29, Register.X29, 0); | ||
| //jalr x0,0(x29) | ||
| EmitJALR(Register.X0, Register.X29, 0); | ||
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| Builder.EmitReloc(symbol, RelocType.IMAGE_REL_BASED_DIR64); | ||
| } | ||
| else | ||
| { | ||
| Builder.EmitUInt(0x00000000); // bad code. | ||
| throw new NotImplementedException(); | ||
| } | ||
| } | ||
|
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| public void EmitRETIfZero(Register regSrc) | ||
| { | ||
| // bne regSrc, x0, 8 | ||
| Builder.EmitUInt((uint)(0x00001463 | ((uint)regSrc << 15))); | ||
| EmitRET(); | ||
| } | ||
|
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| public void EmitJMPIfZero(Register regSrc, ISymbolNode symbol) | ||
| { | ||
| uint offset = symbol.RepresentsIndirectionCell ? 28u : 8u; | ||
| uint encodedOffset = ((offset & 0x1e) << 7) | ((offset & 0x7e0) << 20) | ((offset & 0x800) >> 4) | ((offset & 0x1000) << 19); | ||
| // bne regSrc, x0, offset | ||
| Builder.EmitUInt((uint)(0x00001063 | ((uint)regSrc << 15) | encodedOffset)); | ||
| EmitJMP(symbol); | ||
| } | ||
| } | ||
| } |
38 changes: 38 additions & 0 deletions
38
src/coreclr/tools/Common/Compiler/DependencyAnalysis/Target_RiscV64/TargetRegisterMap.cs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,38 @@ | ||
| // Licensed to the .NET Foundation under one or more agreements. | ||
| // The .NET Foundation licenses this file to you under the MIT license. | ||
|
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| using Internal.TypeSystem; | ||
|
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| namespace ILCompiler.DependencyAnalysis.RiscV64 | ||
| { | ||
| /// <summary> | ||
| /// Maps logical registers to physical registers on a specified OS. | ||
| /// </summary> | ||
| public struct TargetRegisterMap | ||
| { | ||
| public readonly Register Arg0; | ||
| public readonly Register Arg1; | ||
| public readonly Register Arg2; | ||
| public readonly Register Arg3; | ||
| public readonly Register Arg4; | ||
| public readonly Register Arg5; | ||
| public readonly Register Arg6; | ||
| public readonly Register Arg7; | ||
| public readonly Register IntraProcedureCallScratch1; | ||
| public readonly Register Result; | ||
|
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| public TargetRegisterMap(TargetOS os) | ||
| { | ||
| Arg0 = Register.X10; | ||
| Arg1 = Register.X11; | ||
| Arg2 = Register.X12; | ||
| Arg3 = Register.X13; | ||
| Arg4 = Register.X14; | ||
| Arg5 = Register.X15; | ||
| Arg6 = Register.X16; | ||
| Arg7 = Register.X17; | ||
| IntraProcedureCallScratch1 = Register.X28; | ||
| Result = Register.X10; | ||
| } | ||
| } | ||
| } |
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