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* Initial work * Added a comma to display * Cleanup * Fixing build * More cleanup * Update comment * Update comment * Added CompareEqual Vector64/128 with Zero tests * Do not contain op1 for now * Wrong intrinsic id used * Removing generated tests * Removing generated tests * Added CompareEqual tests * Supporting containment for first operand * Fix test build * Passing correct register * Check IsVectorZero before not allocing a register * Update comment * Fixing test * Minor format change * Fixed formatting * Renamed test * Adding AdvSimd_Arm64 tests: * Adding support for rest of 'cmeq' and 'fcmeq' instructions * Removing github csproj * Minor test fix * Fixed tests * Fix print * Minor format change * Fixing test * Initial commit for Vector.Create to Vector.Zero normalization * Added some emitter tests * Feedback * Update emitarm64.cpp * Feedback * Handling variations of Vector.Create * Use Operands iterator instead of edges * Fix condition * Simplify * format * Fixed IsFloatPositiveZero * Uncomment * Updated tests to include Vector64.Create/Vector128.Create for ARM64 * Making implementation of IsFloatPositiveZero explicit * Update src/coreclr/jit/gentree.cpp Co-authored-by: SingleAccretion <62474226+SingleAccretion@users.noreply.github.com> * Feedback * Update comment * Update comment * Do not perform optimization when VN CSE phase * use ResetHWIntrinsicId * Assert !optValnumCSE_phase * Simplify IsVectorZero * Simplify IsVectorZero * Simplify some uses of Vector*_get_Zero * Added another test * Fixed formatting * Revert lowering removal * Update gentree.h * Feedback Co-authored-by: SingleAccretion <62474226+SingleAccretion@users.noreply.github.com>
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