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[release/7.0-preview1] Ensure that we aren't accidentally generating …
…instructions for unsupported ISAs (#64224) * Assert that the ISA of the set intrinsic ID is supported * Ensure gtNewSimdCmpOpAllNode and gtNewSimdCmpOpAnyNode don't generate AVX2 instructions when not supported * Ensure codegen for Vector128.Dot when SSSE3 is disabled is correct * Update src/coreclr/jit/hwintrinsiccodegenarm64.cpp Co-authored-by: Jan Kotas <jkotas@microsoft.com> * Ensure Vector256.Sum has a check for AVX2 Co-authored-by: Tanner Gooding <tagoo@outlook.com> Co-authored-by: Jan Kotas <jkotas@microsoft.com>
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