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Remember to handle IsRegOptional
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tannergooding committed Sep 28, 2022
1 parent 94e17ab commit c3515a8
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Showing 2 changed files with 1 addition and 14 deletions.
13 changes: 0 additions & 13 deletions src/coreclr/jit/codegencommon.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1057,19 +1057,6 @@ bool CodeGen::genCreateAddrMode(
op2 = addr->AsOp()->gtOp2;
}

#if TARGET_ARM64
if (op2->OperIsLIR() && op2->isContained() && op2->OperIs(GT_CAST))
{
*rv1Ptr = op1;
*rv2Ptr = op2;
*mulPtr = 1;
*cnsPtr = 0;
*revPtr = false; // op2 is never a gc type
assert(!varTypeIsGC(op2));
return true;
}
#endif

// Can't use indirect addressing mode as we need to check for overflow.
// Also, can't use 'lea' as it doesn't set the flags.

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2 changes: 1 addition & 1 deletion src/coreclr/jit/lowerarmarch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -288,7 +288,7 @@ bool Lowering::IsContainableBinaryOp(GenTree* parentNode, GenTree* childNode) co
// Find "a op cast(b)"
GenTree* castOp = childNode->AsCast()->CastOp();

if (castOp->isContained())
if (castOp->isContained() || castOp->IsRegOptional())
{
// Cannot contain if the childs op1 is already contained
return false;
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