amend the code for CRs.

dotnet · Jul 26, 2022 · e8115e4 · e8115e4
1 parent b5bb99e
commit e8115e4
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Showing 2 changed files with 52 additions and 46 deletions.
diff --git a/src/coreclr/jit/codegenloongarch64.cpp b/src/coreclr/jit/codegenloongarch64.cpp
@@ -6643,6 +6643,46 @@ void CodeGen::genCodeForLclFld(GenTreeLclFld* tree)
     genProduceReg(tree);
 }
 
+//------------------------------------------------------------------------
+// genScaledAdd: A helper for `dest = base + (index << scale)`
+//               and maybe optimize the instruction(s) for this operation.
+//
+void CodeGen::genScaledAdd(emitAttr attr, regNumber targetReg, regNumber baseReg, regNumber indexReg, int scale)
+{
+    emitter* emit = GetEmitter();
+    if (scale == 0)
+    {
+        instruction ins = attr == EA_4BYTE ? INS_add_w : INS_add_d;
+        // target = base + index
+        emit->emitIns_R_R_R(ins, attr, targetReg, baseReg, indexReg);
+    }
+    else if (scale <= 4)
+    {
+        instruction ins = attr == EA_4BYTE ? INS_alsl_w : INS_alsl_d;
+        // target = base + index << scale
+        emit->emitIns_R_R_R_I(ins, attr, targetReg, indexReg, baseReg, scale - 1);
+    }
+    else
+    {
+        instruction ins;
+        instruction ins2;
+        if (attr == EA_4BYTE)
+        {
+            ins  = INS_slli_w;
+            ins2 = INS_add_w;
+        }
+        else
+        {
+            ins  = INS_slli_d;
+            ins2 = INS_add_d;
+        }
+
+        // target = base + index << scale
+        emit->emitIns_R_R_I(ins, attr, REG_R21, indexReg, scale);
+        emit->emitIns_R_R_R(ins2, attr, targetReg, baseReg, REG_R21);
+    }
+}
+
 //------------------------------------------------------------------------
 // genCodeForIndexAddr: Produce code for a GT_INDEX_ADDR node.
 //
@@ -7078,15 +7118,17 @@ void CodeGen::genCall(GenTreeCall* call)
         else if (abiInfo.IsSplit())
         {
             assert(compFeatureArgSplit());
-            assert(abiInfo.NumRegs == 1);
             genConsumeArgSplitStruct(argNode->AsPutArgSplit());
-            for (unsigned idx = 0; idx < abiInfo.NumRegs; idx++)
-            {
-                regNumber argReg   = (regNumber)((unsigned)abiInfo.GetRegNum() + idx);
-                regNumber allocReg = argNode->AsPutArgSplit()->GetRegNumByIdx(idx);
-                var_types dstType  = emitter::isFloatReg(argReg) ? TYP_DOUBLE : TYP_I_IMPL;
-                inst_Mov(dstType, argReg, allocReg, /* canSkip */ true);
-            }
+
+            regNumber argReg   = (regNumber)((unsigned)abiInfo.GetRegNum() + idx);
+            regNumber allocReg = argNode->AsPutArgSplit()->GetRegNumByIdx(idx);
+
+            // For LA64's ABI, the split is only using the A7 and stack for passing arg.
+            assert(emitter::isGeneralRegister(argReg));
+            assert(emitter::isGeneralRegister(allocReg));
+            assert(abiInfo.NumRegs == 1);
+
+            inst_Mov(TYP_I_IMPL, argReg, allocReg, /* canSkip */ true);
         }
         else
         {
@@ -7972,42 +8014,6 @@ void CodeGen::genCodeForStoreBlk(GenTreeBlk* blkOp)
     }
 }
 
-void CodeGen::genScaledAdd(emitAttr attr, regNumber targetReg, regNumber baseReg, regNumber indexReg, int scale)
-{
-    emitter* emit = GetEmitter();
-    if (scale == 0)
-    {
-        instruction ins = attr == EA_4BYTE ? INS_add_w : INS_add_d;
-        // target = base + index
-        emit->emitIns_R_R_R(ins, attr, targetReg, baseReg, indexReg);
-    }
-    else if (scale <= 4)
-    {
-        instruction ins = attr == EA_4BYTE ? INS_alsl_w : INS_alsl_d;
-        // target = base + index<<scale
-        emit->emitIns_R_R_R_I(ins, attr, targetReg, indexReg, baseReg, scale - 1);
-    }
-    else
-    {
-        instruction ins;
-        instruction ins2;
-        if (attr == EA_4BYTE)
-        {
-            ins  = INS_slli_w;
-            ins2 = INS_add_w;
-        }
-        else
-        {
-            ins  = INS_slli_d;
-            ins2 = INS_add_d;
-        }
-
-        // target = base + index<<scale
-        emit->emitIns_R_R_I(ins, attr, REG_R21, indexReg, scale);
-        emit->emitIns_R_R_R(ins2, attr, targetReg, baseReg, REG_R21);
-    }
-}
-
 //------------------------------------------------------------------------
 // genLeaInstruction: Produce code for a GT_LEA node.
 //

diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
@@ -1162,7 +1162,7 @@ void CallArgABIInformation::SetByteSize(unsigned byteSize, unsigned byteAlignmen
 //   is a HFA of doubles, since double and float registers overlap.
 void CallArgABIInformation::SetMultiRegNums()
 {
-#if FEATURE_MULTIREG_ARGS && !defined(UNIX_AMD64_ABI) && !defined(TARGET_LOONGARCH64)
+#if defined(FEATURE_MULTIREG_ARGS) && !defined(UNIX_AMD64_ABI) && !defined(TARGET_LOONGARCH64)
     if (NumRegs == 1)
     {
         return;
@@ -1183,7 +1183,7 @@ void CallArgABIInformation::SetMultiRegNums()
         argReg = (regNumber)(argReg + regSize);
         SetRegNum(regIndex, argReg);
     }
-#endif // FEATURE_MULTIREG_ARGS && !defined(UNIX_AMD64_ABI) && !defined(TARGET_LOONGARCH64)
+#endif // defined(FEATURE_MULTIREG_ARGS) && !defined(UNIX_AMD64_ABI) && !defined(TARGET_LOONGARCH64)
 }
 
 //---------------------------------------------------------------