Improving ARM64 Performance in .NET 5.0 – Closing the gap with x64

[kunalspathak]

.NET 3.0 was the first release to add support for ARM64, starting with Linux (see ARM64 tracking issue). As part of .NET 5.0, we are adding support for Windows. At this point, we believe that the .NET ARM64 implementation has functional parity with x64 (please report functional bugs!). We’ve since shifted our focus toward performance parity with x64, for Windows and Linux. This issue tracks our progress to achieve that goal. Some of the issues we have identified may broader than ARM64, but still critical performance for our ARM64 performance goals.

Issues	Description	Category	Status
#33308	Optimize library APIs to use ARM64 hardware intrinsics	Libraries	Done
#35108	Indirect call produces redundant address load for R2R	Function call
#36700	Virtual stub call produces redundant address load for R2R / JIT	Function call	Done
#35274	[arm/arm64] Leaf frames, saving LR, and return address hijacking	Function call
#38890	Cache the target of indirect cell address to optimize redundant target loading	Function call
#36663	Dead stores generated from arguments to the dead helper call	Function call
#35631	Unused HFA arguments still get written to stack	Function call	Done
#35635	HFA register arguments pushed to stack	Function call	Done
#35268	Constant pool should share values	General	Done
#34937	Optimize a % b operation for ARM64	General
#35618	Code inefficiencies in loop array indexing	General	Done
#35257	Double constants usage in a loop can be CSEed	General
#35976	Vector64 is converted to HVA TYP_DOUBLE	General	Done
#35622	Addressing mode inefficiencies in Guid:op_Equality(Guid,Guid):bool	Addressing mode
#34810	ARM64: Post index addressing mode	Addressing mode
#35141	Optimize redundant memory loads with mov	Peep-hole optimization
#35071	Redundant load/stores for methods that operates/returns structs	Peep-hole optimization	Dup of #53956
#35136	Optimize pair of "str wzr, [reg]" to "str xzr"	Peep-hole optimization
#35134	Optimize pair of "str reg, [fp]" to stp	Peep-hole optimization
#35133	Optimize pair of "str reg, [reg]" to stp	Peep-hole optimization
#35132	Optimize pair of "ldr reg, [reg]" to ldp	Peep-hole optimization
#35130	Optimize pair of "ldr reg, [fp]" to ldp	Peep-hole optimization
#35252	Redundant movs can be eliminiated	Peep-hole optimization	Done
#35254	Redundant movs done for zero extend the register	Peep-hole optimization	Done
#35614	Remove redundant store that is immediately after the load in same src/dst	Peep-hole optimization	Done
#35613	Remove redundant load that is immediately after the store in same src/dst	Peep-hole optimization	Done

category:cq
theme:meta
skill-level:expert
cost:large

[BruceForstall]

I added this to area-CodeGen-coreclr since most items here are (currently) JIT-related. However, area-Meta might be more appropriate long-term.

[AndyAyersMS]

@kunalspathak if there's no more planned 5.0 work, we should move this to future.

[kunalspathak]

@kunalspathak if there's no more planned 5.0 work, we should move this to future.

Done.

[xiangzhai]

:gsvm-interest