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Assertion failed 'unused->OperIs(GT_CNS_INT)' #77152

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markples opened this issue Oct 18, 2022 · 6 comments · Fixed by #77872
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Assertion failed 'unused->OperIs(GT_CNS_INT)' #77152

markples opened this issue Oct 18, 2022 · 6 comments · Fixed by #77872
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@BruceForstall
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arch-x86 area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI blocking-clean-ci-optional Blocking optional rolling runs in-pr There is an active PR which will close this issue when it is merged JitStress CLR JIT issues involving JIT internal stress modes
Milestone
8.0.0

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@markples
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markples commented Oct 18, 2022 •
edited by BruceForstall
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runtime-coreclr jitstress-random
coreclr Pri1 Runtime Tests Run windows x86 checked

[updated] https://dev.azure.com/dnceng-public/public/_build/results?buildId=54121&view=logs&j=9c28ef9e-8a10-596f-95ff-bea6927d5d94&t=14c2c9a6-52b0-53ea-b9dd-44cd3ba342a9
https://helixre107v0xdeko0k025g8.blob.core.windows.net/dotnet-runtime-refs-heads-main-7d574e4ebff54bd58d/JIT.Regression/1/console.f4fb506d.log?helixlogtype=result

C:\h\w\B99D09C2\w\ABDA09BD\e>type C:\h\w\B99D09C2\w\ABDA09BD\u\SetStressModes_jitstress_random_2.cmd 
set COMPlus_TieredCompilation=0
set COMPlus_JitStress=374
...
    JIT\Regression\JitBlue\Runtime_75312\Runtime_75312\Runtime_75312.cmd [FAIL]
      
      Assert failure(PID 1852 [0x0000073c], Thread: 2244 [0x08c4]): Assertion failed 'unused->OperIs(GT_CNS_INT)' in 'Runtime_75312:Test(int):int' during 'Lowering nodeinfo' (IL size 12; hash 0x98ca5083; MinOpts)
      
          File: D:\a\_work\1\s\src\coreclr\jit\lower.cpp Line: 5421
          Image: C:\h\w\B99D09C2\p\corerun.exe

cc @dotnet/jit-contrib
@markples markples added area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI blocking-clean-ci-optional Blocking optional rolling runs labels Oct 18, 2022
@markples markples added this to the 8.0.0 milestone Oct 18, 2022
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ghost commented Oct 18, 2022

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Issue Details

runtime-coreclr jitstress-random
coreclr Pri1 Runtime Tests Run windows arm64 checked

https://dev.azure.com/dnceng-public/public/_build/results?buildId=54121&view=logs&j=63f2a02a-7891-5505-e9da-45b13105e16b&t=af4e7a65-4894-5021-63d1-400b0a3e36a0
https://helixre107v0xdeko0k025g8.blob.core.windows.net/dotnet-runtime-refs-heads-main-7d574e4ebff54bd58d/JIT.Regression/1/console.f4fb506d.log?helixlogtype=result

C:\h\w\B99D09C2\w\ABDA09BD\e>type C:\h\w\B99D09C2\w\ABDA09BD\u\SetStressModes_jitstress_random_2.cmd 
set COMPlus_TieredCompilation=0
set COMPlus_JitStress=374
...
    JIT\Regression\JitBlue\Runtime_75312\Runtime_75312\Runtime_75312.cmd [FAIL]
      
      Assert failure(PID 1852 [0x0000073c], Thread: 2244 [0x08c4]): Assertion failed 'unused->OperIs(GT_CNS_INT)' in 'Runtime_75312:Test(int):int' during 'Lowering nodeinfo' (IL size 12; hash 0x98ca5083; MinOpts)
      
          File: D:\a\_work\1\s\src\coreclr\jit\lower.cpp Line: 5421
          Image: C:\h\w\B99D09C2\p\corerun.exe

cc @dotnet/jit-contrib

Author: markples
Assignees: -
Labels:

area-CodeGen-coreclr, blocking-clean-ci-optional
Milestone: 8.0.0

@runfoapp runfoapp bot mentioned this issue Oct 18, 2022
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@BruceForstall
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There's some confusion in this bug report. The arm64 link is to a GitHub_23159 failure, previously opened as #76880 and now fixed.

The assert above is from an x86 run.

@BruceForstall BruceForstall added arch-x86 JitStress CLR JIT issues involving JIT internal stress modes labels Nov 2, 2022
@BruceForstall
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TryCreateAddrMode, after parsing a tree and finding an address mode, deletes all the nodes that are no longer needed because they've been converted into the address mode base/index/scale/offset values. It expects the only node types it will find when doing this deletion are GT_ADD, GT_MUL, GT_LSH, and GT_CNS_INT. In the failure case, we have a GT_MUL with op2 of zero, and a complex op1 with stress-introduced GT_CAST nodes. Since the GT_MUL op2 is zero, the code looking for a scale doesn't even look at op1.

The question is whether for GT_MUL(x, 0), can x be an arbitrary IR tree?

@BruceForstall
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The (pre-lower) stress-generated tree here is:

N015 ( 15, 15) [000010] ---XG------                         *  RETURN    int
N014 ( 14, 14) [000009] ---XG------                         \--*  IND       int
N013 ( 13, 13) [000008] -------N---                            \--*  ADD       int
N011 ( 12, 12) [000006] -------N---                               +--*  ADD       int
N001 (  3,  2) [000000] -----------                               |  +--*  LCL_VAR   int    V00 arg0
N010 (  9, 10) [000005] -------N---                               |  \--*  LSH       int
N008 (  8,  9) [000003] -----------                               |     +--*  MUL       int
N005 (  3,  5) [000016] -----------                               |     |  +--*  CAST      int <- long
N004 (  2,  3) [000012] -----------                               |     |  |  \--*  NOP       long
N003 (  2,  3) [000011] -----------                               |     |  |     \--*  CAST      long <- int
N002 (  1,  1) [000001] -----------                               |     |  |        \--*  CNS_INT   int    3
N007 (  1,  1) [000014] -----------                               |     |  \--*  NOP       int
N006 (  1,  1) [000002] -----------                               |     |     \--*  CNS_INT   int    0
N009 (  1,  1) [000004] -----------                               |     \--*  CNS_INT   int    2
N012 (  1,  1) [000007] -----------                               \--*  CNS_INT   int    1

@BruceForstall
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Long decomposition inserts a temp for the "GT_CAST(long<-int)(GT_CNS_INT(3))" which makes it even more complex:

               [000020] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  3,  2) [000000] -c---------                    t0 =    LCL_VAR   int    V00 arg0
N002 (  1,  1) [000001] -c---------                    t1 =    CNS_INT   int    3
                                                            /--*  t1     int
               [000022] DA---------                         *  STORE_LCL_VAR int    V01 tmp0
               [000023] -----------                   t23 =    LCL_VAR   int    V01 tmp0
               [000024] -----------                   t24 =    LCL_VAR   int    V01 tmp0
               [000025] -c---------                   t25 =    CNS_INT   int    31
                                                            /--*  t24    int
                                                            +--*  t25    int
               [000026] -----------                   t26 = *  RSH       int
                                                            /--*  t23    int
                                                            +--*  t26    int
               [000027] -c---------                   t27 = *  LONG      long
                                                            /--*  t27    long
N005 (  3,  5) [000016] -----------                   t16 = *  CAST      int <- long
N006 (  1,  1) [000002] -c---------                    t2 =    CNS_INT   int    0
                                                            /--*  t16    int
                                                            +--*  t2     int
N008 (  8,  9) [000003] -----------                    t3 = *  MUL       int
N009 (  1,  1) [000004] -c---------                    t4 =    CNS_INT   int    2
                                                            /--*  t3     int
                                                            +--*  t4     int
N010 (  9, 10) [000005] -------N---                    t5 = *  LSH       int
                                                            /--*  t0     int
                                                            +--*  t5     int
N011 ( 12, 12) [000006] -------N---                    t6 = *  ADD       int
N012 (  1,  1) [000007] -c---------                    t7 =    CNS_INT   int    1
                                                            /--*  t6     int
                                                            +--*  t7     int
N013 ( 13, 13) [000008] -------N---                    t8 = *  ADD       int
                                                            /--*  t8     int
N014 ( 14, 14) [000009] ---XG------                    t9 = *  IND       int
                                                            /--*  t9     int
N015 ( 15, 15) [000010] ---XG------                         *  RETURN    int

@BruceForstall
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This is all due to STRESS_64RSLT_MUL

BruceForstall added a commit to BruceForstall/runtime that referenced this issue Nov 3, 2022
@BruceForstall
Fix STRESS_64RSLT_MUL stress mode to avoid creating unnecessary IR
e0a3fcd 
Issue dotnet#77152 is an assert
in unoptimized code where the IR constructs an addressing mode
from a tree including a GT_MUL with op2 of zero, hence it ignores
op1, but then asserts because it only expects a limited set of
IR nodes to be in the op1 tree.

This fixes this one particular case by avoiding creating the extra
nodes in this stress mode. In normal optimized code, the MUL with
zero would be folded.

Fixes dotnet#77152
@BruceForstall BruceForstall mentioned this issue Nov 3, 2022
Closed
@ghost ghost added the in-pr There is an active PR which will close this issue when it is merged label Nov 3, 2022
@BruceForstall BruceForstall mentioned this issue Nov 3, 2022
Merged
BruceForstall added a commit to BruceForstall/runtime that referenced this issue Nov 6, 2022
@BruceForstall
Allow deleting any kind of nodes after address mode formation
4afac32 
This is a general solution to dotnet#77152, allowing for deleting any
set of nodes that contributed to an address mode, especially those
nodes on the `op1` side of a GT_MUL with a zero `op2`.

Note that for the dotnet#77152 case, this deletes all the `op1` nodes,
but leaves behind a dead temp var that was created as part of
long MUL rationalization.

Fixes dotnet#77152.
BruceForstall added a commit that referenced this issue Nov 7, 2022
@BruceForstall
Allow deleting any kind of nodes after address mode formation (#77872)
c6549d9 
* Allow deleting any kind of nodes after address mode formation

This is a general solution to #77152, allowing for deleting any
set of nodes that contributed to an address mode, especially those
nodes on the `op1` side of a GT_MUL with a zero `op2`.

Note that for the #77152 case, this deletes all the `op1` nodes,
but leaves behind a dead temp var that was created as part of
long MUL rationalization.

Fixes #77152.

* Add DEBUG_DESTROY_NODE
@ghost ghost locked as resolved and limited conversation to collaborators Dec 8, 2022
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Labels
arch-x86 area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI blocking-clean-ci-optional Blocking optional rolling runs in-pr There is an active PR which will close this issue when it is merged JitStress CLR JIT issues involving JIT internal stress modes
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Milestone
8.0.0
2 participants
@BruceForstall @markples