[mono] fix SIMD instructions' availability

[EgorBo]

Fixes: #34304

@tannergooding @davidwrighton
Now it fully matches clang/LLVM behavior, e.g. even -mattr=+avx2 (or -mavx2 in clang) doesn't enable pcmul and aes. However, -mattr=+sse4.2 (-msse4.2) enables popcnt (see https://godbolt.org/z/RWAp_D). The intel manual says

So is there a CPU with AVX set but without popcnt? The instruction is pretty useful (it is used in BCL) users might forget to define it when they use mattr=avx (or mattr=avx2).

However in C++ world programmers use named groups e.g. mcpu=haswell rather than listing these sets via attributes.

[tannergooding]

So is there a CPU with AVX set but without popcnt?

I would expect that this wouldn't happen in practice, but I think it is still appropriate to model the underlying checks accurately so we aren't stuck with a breaking change in the future if that ever changes.

For Intel, POPCNT was introduced as part of SSE4.2 (2008, Nehalem), but it is a separate CPUID check because AMD had already introduced POPCNT and LZCNT independently as part of ABM (2007, Barcelona). Intel didn't introduce LZCNT until much later alongside AVX2/BMI1/BMI2/FMA3 (2013, Haswell).

[tannergooding]

This name is a bit confusing, I'm not quite sure based on the name along, what is meant to be enabled by it.

[EgorBo]

@tannergooding it's only used internally to be able to disable SSE/AVX like that:
mattr=-sse3 => disable sse3, also ssse3, sse4.1, etc (but don't touch lzcnt, bmi)

see here: https://github.com/dotnet/runtime/blob/master/src/mono/mono/mini/aot-compiler.c#L8109-L8111

it also matches llvm behaviour.

[EgorBo]

it allows to do things like this mcpu=native,mattr=-avx

[tannergooding]

LGTM and to match the hierarchy specified by the Intel/AMD architecture manuals.

[EgorBo]

The failing job is known and unrelated