Ensure we mark op2 as delayFree if it is rmw and the parent node returns a non-SIMD type

[tannergooding]

This resolves #36198

We were missing the scenario where the intrinsic is RMW, op2 was contained, and where the parent node produces a non-SIMD result. In that scenario, the contained node may use a register from the same set as the target operand, in which case we need op2 to be delay free.

[tannergooding]

CC. @CarolEidt, @echesakovMSFT, @kunalspathak

[tannergooding]

This wasn't failing for 32-bit because we have special handling here to account for only RBM_BYTE_REGS being allowed for use as byte registers (according to the comment at least): https://github.com/dotnet/runtime/blob/master/src/coreclr/src/jit/lsraxarch.cpp#L2487-L2506

[CarolEidt]

LGTM - thanks!

[echesakov]

@tannergooding I didn't understand the issue description:

We were missing the scenario where the intrinsic is RMW, op2 was contained, and where the parent node produces a non-SIMD result. In that scenario, the contained node may use a register from the same set as the target operand, in which case we need op2 to be delay free.

Can you please explain how contained op2 may use a register? My understanding if op2 is contained it doesn't need a register since it's computed as a part of the parent node. An example of such situation would also be helpful

[CarolEidt]

Can you please explain how contained op2 may use a register?

A contained op2 can be an addressing mode that uses a base and/or index register.

[echesakov]

@CarolEidt Thanks,make sense

[tannergooding]

Right, the x86 addressing mode allows for [baseReg + indexReg * scale].

We had Sse42.Crc32(0xffffffffU, *ptr), and were generating

       488B7D60             mov      rdi, qword ptr [rbp+60H]
       BEFFFFFFFF           mov      esi, -1
       8BFE                 mov      edi, esi
       F2400F38F03F         crc32    edi, byte  ptr [rdi]

[ghost]

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