[RISC-V][JIT] JIT/CodeGenBringUpTest #84748

clamp03 · 2023-04-13T01:29:05Z

JIT/CodeGenBringupTest tests passed

Implemented some NYI functions
Updated Floating Point Rounding Mode, Compare and JumpCompare
Updated Arguments Handling in Prolog
Fix some bugs in making constant values
A sub task of CoreCLR RISC-V architecture port #84834
~~Some tests failed with CHECKED or RELEASE build.~~

- Update Floating Point Compare - Implement NYI functions

- Implement NYI functions

- Update genFnPrologCalleeRegArgs

Fix an error in ./JIT/CodeGenBringUpTests/struct16args_d/struct16args_d.sh

Fixed erros in belows ./JIT/CodeGenBringUpTests/Rotate_d/Rotate_d.sh ./JIT/CodeGenBringUpTests/Rotate_do/Rotate_do.sh ./JIT/CodeGenBringUpTests/Rotate_r/Rotate_r.sh ./JIT/CodeGenBringUpTests/Rotate_ro/Rotate_ro.sh

Resolve ``` ./JIT/CodeGenBringUpTests/JTrueNeFP_do/JTrueNeFP_do.sh ./JIT/CodeGenBringUpTests/JTrueNeFP_d/JTrueNeFP_d.sh ./JIT/CodeGenBringUpTests/JTrueNeFP_r/JTrueNeFP_r.sh ./JIT/CodeGenBringUpTests/JTrueNeFP_ro/JTrueNeFP_ro.sh ```

Add a missed part for making constant. In the cases, it is -12. Resolved ./JIT/CodeGenBringUpTests/NegRMW_do/NegRMW_do.sh ./JIT/CodeGenBringUpTests/NegRMW_ro/NegRMW_ro.sh

TODO-RISCV64: We should optimize constant and address construction.

- Change fcvt to fmv in ins_Copy

- Add rounding mode

- Add Neg for float - Add rounding mode in float arithmetic

- remove dead code

ghost · 2023-04-13T01:29:17Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch, @kunalspathak
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Issue Details

Fixed errors in JIT for JIT/CodeGenBringupTest

With DEBUG build, all JIT/CodeGenBringupTest tests passed with [RISC-V] coreclr-pal and coreclr-debug directories #82380 and [RISC-V] coreclr-vm and other directories in coreclr #82381
Implemented some NYI functions
Updated Floating Point Rounding Mode, Compare and JumpCompare
Updated Arguments Handling in Prolog
Fix some bugs in making constant values
Some tests failed with CHECKED or RELEASE build.

Author:	clamp03
Assignees:	-
Labels:	`area-CodeGen-coreclr`, `community-contribution`
Milestone:	-

clamp03

I need helps and reviews.

src/coreclr/jit/emitriscv64.cpp

clamp03 · 2023-04-13T01:34:43Z

src/coreclr/jit/emitriscv64.cpp

@@ -1087,45 +1112,56 @@ void emitter::emitIns_I_la(emitAttr size, regNumber reg, ssize_t imm)
 {


I updated a emitIns_I_la which make a constant value. However, I think there is better solution for emitIns_I_la. If you have any idea, please help me! Thank you.

It can be optimized later, when the RISC-V codes are ready to go into the optimizing phase.

For other platforms we have instGen_Set_Reg_To_Imm which is responsible for emitting the instructions to set a register to an arbitrarily sized immediate. However, it lives in CodeGen.

I can see that the emitIns_I_la is used for some contained addresses with large offsets that need to be first materialized into a register. In general, it would be better to avoid containing these addresses in the first place as it misses the point of containment, which is that the parent node can more efficiently handle the codegen of the child node. If the codegen is going to materialize the value into a register anyway, then there is no reason to mark it contained in the first place.

I see. Next time, I will update emitIns_I_la to instGen_Set_Reg_To_Imm and check containment on RISC-V.
Thank you!

clamp03 · 2023-04-13T01:36:57Z

CC @wscho77 @HJLeee @JongHeonChoi @gbalykov @t-mustafin

clamp03 · 2023-04-13T05:26:07Z

Build failure will be resolved by #82381. Until then, put [WIP] in the title.

- Reverse JCMP cond for reversing jump opt

This reverts commit bed8b9c.

alpencolt · 2023-04-27T16:09:34Z

Could this PR be merged?

jakobbotsch · 2023-04-27T17:08:40Z

src/coreclr/jit/codegenriscv64.cpp

@@ -3327,7 +3351,88 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
    if (varTypeIsFloating(op1Type))
    {
        assert(tree->OperIs(GT_LT, GT_LE, GT_EQ, GT_NE, GT_GT, GT_GE));
-        NYI_RISCV64("genCodeForCompare-----unimplemented on RISCV64 yet----");
+        bool      IsUnordered = (tree->gtFlags & GTF_RELOP_NAN_UN) != 0;


This is wrong naming conventions (should be isUnordered), but let's not hold this PR up on it.

Thank you! I will fix in the next PR.

clamp03 and others added 22 commits April 11, 2023 18:41

[JIT] Update RISCV64

9539195

- Update Floating Point Compare - Implement NYI functions

[JIT] Update RISCV64

f77a71f

- Implement NYI functions

[JIT] FIX TEST ERRORS

34ba039

- Implement NYI functions

[JIT] FIX TEST ERROR

8093fdd

- Update genFnPrologCalleeRegArgs

[JIT] FIX TEST ERRORS

2a47ddd

[JIT] FIX TEST ERROR

3b698f5

Fix an error in ./JIT/CodeGenBringUpTests/struct16args_d/struct16args_d.sh

[JIT] Fix rotate test errors

759a461

Fixed erros in belows ./JIT/CodeGenBringUpTests/Rotate_d/Rotate_d.sh ./JIT/CodeGenBringUpTests/Rotate_do/Rotate_do.sh ./JIT/CodeGenBringUpTests/Rotate_r/Rotate_r.sh ./JIT/CodeGenBringUpTests/Rotate_ro/Rotate_ro.sh

[JIT] Fix erorrs in JTrueNeFP

b36c0cd

Resolve ``` ./JIT/CodeGenBringUpTests/JTrueNeFP_do/JTrueNeFP_do.sh ./JIT/CodeGenBringUpTests/JTrueNeFP_d/JTrueNeFP_d.sh ./JIT/CodeGenBringUpTests/JTrueNeFP_r/JTrueNeFP_r.sh ./JIT/CodeGenBringUpTests/JTrueNeFP_ro/JTrueNeFP_ro.sh ```

[JIT] Fix an error

3fbdff4

Add a missed part for making constant. In the cases, it is -12. Resolved ./JIT/CodeGenBringUpTests/NegRMW_do/NegRMW_do.sh ./JIT/CodeGenBringUpTests/NegRMW_ro/NegRMW_ro.sh

[JIT] Optimize making constant a little

c401dff

TODO-RISCV64: We should optimize constant and address construction.

[JIT] Update emitIns_I_la more

49b4952

Add todo comment about code quality

cf897f6

[JIT] Fix bugs in float and double

549ee14

- Change fcvt to fmv in ins_Copy

[JIT] Remove unnecessary comment

f2336ca

[JIT] FIX

b9ff4f0

- Add rounding mode

[JIT] Fix error

36b4b35

- Add Neg for float - Add rounding mode in float arithmetic

[JIT] Update Float Neg

478110e

[JIT] Update rounding mode and register use

268cf41

[JIT] Update

89b0adb

- remove dead code

[JIT] Support Float JumpCompare

f91f640

[JIT] Remove GT_OBJ and LCL_VAR_ADDR

c2c89a3

[JIT] JIT-FORMAT

4eec2be

ghost added the community-contribution Indicates that the PR has been added by a community member label Apr 13, 2023

dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Apr 13, 2023

clamp03 commented Apr 13, 2023

View reviewed changes

clamp03 changed the title ~~[RISC-V][JIT] JIT/CodeGenBringUpTest~~ [WIP][RISC-V][JIT] JIT/CodeGenBringUpTest Apr 13, 2023

[JIT] Fix JCMP cond error

bed8b9c

- Reverse JCMP cond for reversing jump opt

build-analysis bot mentioned this pull request Apr 13, 2023

jitformat failing on linux x64 #84780

Closed

gbalykov mentioned this pull request Apr 14, 2023

CoreCLR RISC-V architecture port #84834

Open

7 tasks

clamp03 changed the title ~~[WIP][RISC-V][JIT] JIT/CodeGenBringUpTest~~ [RISC-V][JIT] JIT/CodeGenBringUpTest Apr 15, 2023

Merge remote-tracking branch 'upstream/main' into codegenbringuptest

6c57087

build-analysis bot mentioned this pull request Apr 17, 2023

Tracking issue for CI build timeouts #76454

Closed

clamp03 added 6 commits April 24, 2023 09:31

Merge remote-tracking branch 'upstream/main' into codegenbringuptest

8ec1c58

Revert "[JIT] Fix JCMP cond error"

af68827

This reverts commit bed8b9c.

Merge remote-tracking branch 'upstream/main' into codegenbringuptest

5520585

[JIT] Remove rounding mode comments

1946f91

[JIT] Fix Float-to-Float copy

5a52b0e

Update Alignment and Definitions

278a490

jakobbotsch reviewed Apr 27, 2023

View reviewed changes

jakobbotsch approved these changes Apr 27, 2023

View reviewed changes

jakobbotsch merged commit 4dbaddb into dotnet:main Apr 27, 2023

clamp03 deleted the codegenbringuptest branch April 28, 2023 04:08

am11 added the arch-riscv Related to the RISC-V architecture label May 13, 2023

ghost locked as resolved and limited conversation to collaborators Jun 12, 2023

clamp03 self-assigned this Sep 7, 2023

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[RISC-V][JIT] JIT/CodeGenBringUpTest #84748

[RISC-V][JIT] JIT/CodeGenBringUpTest #84748

clamp03 commented Apr 13, 2023 •

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clamp03 commented Apr 13, 2023 •

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alpencolt commented Apr 27, 2023

jakobbotsch Apr 27, 2023

clamp03 Apr 28, 2023

		@@ -1087,45 +1112,56 @@ void emitter::emitIns_I_la(emitAttr size, regNumber reg, ssize_t imm)
		{

[RISC-V][JIT] JIT/CodeGenBringUpTest #84748

[RISC-V][JIT] JIT/CodeGenBringUpTest #84748

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