[RISC-V] Fix Shuffling Thunks part 2 #90707
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| Original file line number | Diff line number | Diff line change |
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@@ -1081,96 +1081,92 @@ void StubLinkerCPU::EmitMovConstant(IntReg reg, UINT64 imm) | |
| } | ||
| } | ||
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| void StubLinkerCPU::EmitJumpRegister(IntReg regTarget) | ||
| { | ||
| Emit32(0x00000067 | (regTarget << 15)); | ||
| } | ||
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| // Instruction types as per RISC-V Spec, Chapter 24 RV32/64G Instruction Set Listings | ||
| static unsigned ITypeInstr(unsigned opcode, unsigned funct3, unsigned rd, unsigned rs1, int imm12) | ||
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There was a problem hiding this comment.
There was a problem hiding this comment. Can be moved. Since I'm fairly new to the codebase, what's a good place to put code shared between VM and JIT? There's some more redundancy between the JIT and VM emitter code, e.g. There was a problem hiding this comment.
There was a problem hiding this comment. The duplication of instruction encoding helpers is very small and it is there on all platforms. I do not think that it is worth fixing. The instruction encoding support in the JIT has to support nearly all instruction. The stublinker needs to be able to encode just a few instructions and so it can be very simple. |
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| { | ||
| _ASSERTE(!(opcode >> 7)); | ||
| _ASSERTE(!(funct3 >> 3)); | ||
| _ASSERTE(!(rd >> 5)); | ||
| _ASSERTE(!(rs1 >> 5)); | ||
| _ASSERTE(StubLinkerCPU::isValidSimm12(imm12)); | ||
| return opcode | (rd << 7) | (funct3 << 12) | (rs1 << 15) | (imm12 << 20); | ||
| } | ||
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| static unsigned STypeInstr(unsigned opcode, unsigned funct3, unsigned rs1, unsigned rs2, int imm12) | ||
| { | ||
| _ASSERTE(!(opcode >> 7)); | ||
| _ASSERTE(!(funct3 >> 3)); | ||
| _ASSERTE(!(rs1 >> 5)); | ||
| _ASSERTE(!(rs2 >> 5)); | ||
| _ASSERTE(StubLinkerCPU::isValidSimm12(imm12)); | ||
| int immLo5 = imm12 & 0x1f; | ||
| int immHi7 = (imm12 >> 5) & 0x7f; | ||
| return opcode | (immLo5 << 7) | (funct3 << 12) | (rs1 << 15) | (rs2 << 20) | (immHi7 << 25); | ||
| } | ||
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| static unsigned RTypeInstr(unsigned opcode, unsigned funct3, unsigned funct7, unsigned rd, unsigned rs1, unsigned rs2) | ||
| { | ||
| _ASSERTE(!(opcode >> 7)); | ||
| _ASSERTE(!(funct3 >> 3)); | ||
| _ASSERTE(!(funct7 >> 7)); | ||
| _ASSERTE(!(rd >> 5)); | ||
| _ASSERTE(!(rs1 >> 5)); | ||
| _ASSERTE(!(rs2 >> 5)); | ||
| return opcode | (rd << 7) | (funct3 << 12) | (rs1 << 15) | (rs2 << 20) | (funct7 << 25); | ||
| } | ||
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| void StubLinkerCPU::EmitLoad(IntReg dest, IntReg srcAddr, int offset) | ||
| { | ||
| Emit32(ITypeInstr(0x3, 0x3, dest, srcAddr, offset)); // ld | ||
| } | ||
| void StubLinkerCPU::EmitLoad(FloatReg dest, IntReg srcAddr, int offset) | ||
| { | ||
| Emit32(ITypeInstr(0x7, 0x3, dest, srcAddr, offset)); // fld | ||
| } | ||
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| void StubLinkerCPU:: EmitStore(IntReg src, IntReg destAddr, int offset) | ||
| { | ||
| Emit32(STypeInstr(0x23, 0x3, destAddr, src, offset)); // sd | ||
| } | ||
| void StubLinkerCPU::EmitStore(FloatReg src, IntReg destAddr, int offset) | ||
| { | ||
| Emit32(STypeInstr(0x27, 0x3, destAddr, src, offset)); // fsd | ||
| } | ||
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| void StubLinkerCPU::EmitMovReg(IntReg Xd, IntReg Xm) | ||
| { | ||
| EmitAddImm(Xd, Xm, 0); | ||
| } | ||
| void StubLinkerCPU::EmitMovReg(FloatReg dest, FloatReg source) | ||
| { | ||
| Emit32(RTypeInstr(0x53, 0, 0x11, dest, source, source)); // fsgnj.d | ||
| } | ||
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| void StubLinkerCPU::EmitSubImm(IntReg Xd, IntReg Xn, unsigned int value) | ||
| { | ||
| _ASSERTE(value <= 0x800); | ||
| EmitAddImm(Xd, Xn, ~value + 0x1); | ||
| } | ||
| void StubLinkerCPU::EmitAddImm(IntReg Xd, IntReg Xn, unsigned int value) | ||
| { | ||
| Emit32(ITypeInstr(0x13, 0, Xd, Xn, value)); // addi | ||
| } | ||
| void StubLinkerCPU::EmitSllImm(IntReg Xd, IntReg Xn, unsigned int value) | ||
| { | ||
| _ASSERTE(!(value >> 6)); | ||
| Emit32(ITypeInstr(0x13, 0x1, Xd, Xn, value)); // slli | ||
| } | ||
| void StubLinkerCPU::EmitLuImm(IntReg Xd, unsigned int value) | ||
| { | ||
| _ASSERTE(value <= 0xFFFFF); | ||
| Emit32((DWORD)(0x00000037 | (value << 12) | (Xd << 7))); // lui Xd, value | ||
| } | ||
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| void StubLinkerCPU::Init() | ||
| { | ||
| new (gBranchIF) BranchInstructionFormat(); | ||
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@@ -1179,12 +1175,13 @@ void StubLinkerCPU::Init() | |
| // Emits code to adjust arguments for static delegate target. | ||
| VOID StubLinkerCPU::EmitShuffleThunk(ShuffleEntry *pShuffleEntryArray) | ||
| { | ||
| static const int argRegBase = 10; // first argument register: a0, fa0 | ||
| static const IntReg t6 = 31, t5 = 30, a0 = argRegBase + 0; | ||
| // On entry a0 holds the delegate instance. Look up the real target address stored in the MethodPtrAux | ||
| // field and saved in t6. Tailcall to the target method after re-arranging the arguments | ||
| EmitLoad(t6, a0, DelegateObject::GetOffsetOfMethodPtrAux()); | ||
| // load the indirection cell into t5 used by ResolveWorkerAsmStub | ||
| EmitAddImm(t5, a0, DelegateObject::GetOffsetOfMethodPtrAux()); | ||
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| int delay_index[8] = {-1}; | ||
| bool is_store = false; | ||
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@@ -1204,23 +1201,19 @@ VOID StubLinkerCPU::EmitShuffleThunk(ShuffleEntry *pShuffleEntryArray) | |
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| if (pEntry->srcofs & ShuffleEntry::FPREGMASK) | ||
| { | ||
| int j = 1; | ||
| while (pEntry[j].srcofs & ShuffleEntry::FPREGMASK) | ||
| { | ||
| j++; | ||
| } | ||
| assert((pEntry->dstofs - pEntry->srcofs) == index); | ||
| assert(8 > index); | ||
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| int tmp_reg = 0; // ft0. | ||
| ShuffleEntry* tmp_entry = pShuffleEntryArray + delay_index[0]; | ||
| while (index) | ||
| { | ||
| EmitLoad(FloatReg(tmp_reg), RegSp, tmp_entry->srcofs * sizeof(void*)); | ||
| tmp_reg++; | ||
| index--; | ||
| tmp_entry++; | ||
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@@ -1231,72 +1224,72 @@ VOID StubLinkerCPU::EmitShuffleThunk(ShuffleEntry *pShuffleEntryArray) | |
| i += j; | ||
| while (pEntry[j].srcofs & ShuffleEntry::FPREGMASK) | ||
| { | ||
| FloatReg src = (pEntry[j].srcofs & ShuffleEntry::OFSREGMASK) + argRegBase; | ||
| if (pEntry[j].dstofs & ShuffleEntry::FPREGMASK) { | ||
| FloatReg dst = (pEntry[j].dstofs & ShuffleEntry::OFSREGMASK) + argRegBase; | ||
| EmitMovReg(dst, src); | ||
| } | ||
| else | ||
| { | ||
| EmitStore(src, RegSp, pEntry[j].dstofs * sizeof(void*)); | ||
| } | ||
| j--; | ||
| } | ||
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| assert(tmp_reg <= 7); | ||
| while (tmp_reg > 0) | ||
| { | ||
| tmp_reg--; | ||
| EmitMovReg(FloatReg(index + argRegBase), FloatReg(tmp_reg)); | ||
| index++; | ||
| } | ||
| index = 0; | ||
| pEntry = tmp_entry; | ||
| } | ||
| else | ||
| { | ||
| assert(pEntry->dstofs & ShuffleEntry::REGMASK); | ||
| IntReg dst = (pEntry->dstofs & ShuffleEntry::OFSREGMASK) + argRegBase; | ||
| IntReg src = (pEntry->srcofs & ShuffleEntry::OFSREGMASK) + argRegBase; | ||
| assert(dst < src); | ||
| EmitMovReg(dst, src); | ||
| } | ||
| } | ||
| else if (pEntry->dstofs & ShuffleEntry::REGMASK) | ||
| { | ||
| // source must be on the stack | ||
| _ASSERTE(!(pEntry->srcofs & ShuffleEntry::REGMASK)); | ||
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| int dstReg = (pEntry->dstofs & ShuffleEntry::OFSREGMASK) + argRegBase; | ||
| int srcOfs = (pEntry->srcofs & ShuffleEntry::OFSMASK) * sizeof(void*); | ||
| if (pEntry->dstofs & ShuffleEntry::FPREGMASK) | ||
| { | ||
| if (!is_store) | ||
| { | ||
| delay_index[index++] = i; | ||
| continue; | ||
| } | ||
| EmitLoad(FloatReg(dstReg), RegSp, srcOfs); | ||
| } | ||
| else | ||
| { | ||
| EmitLoad(IntReg(dstReg), RegSp, srcOfs); | ||
| } | ||
| } | ||
| else | ||
| { | ||
| // source & dest must be on the stack | ||
| _ASSERTE(!(pEntry->srcofs & ShuffleEntry::REGMASK)); | ||
| _ASSERTE(!(pEntry->dstofs & ShuffleEntry::REGMASK)); | ||
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| IntReg t4 = 29; | ||
| EmitLoad(t4, RegSp, pEntry->srcofs * sizeof(void*)); | ||
| EmitStore(t4, RegSp, pEntry->dstofs * sizeof(void*)); | ||
| } | ||
| } | ||
| // Tailcall to target | ||
| // jalr x0, 0(t6) | ||
| EmitJumpRegister(t6); | ||
| } | ||
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| // Emits code to adjust arguments for static delegate target. | ||
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@@ -1334,7 +1327,7 @@ VOID StubLinkerCPU::EmitComputedInstantiatingMethodStub(MethodDesc* pSharedMD, s | |
| // Unboxing stub case | ||
| // Fill param arg with methodtable of this pointer | ||
| // ld regHidden, a0, 0 | ||
| EmitLoad(IntReg(regHidden), IntReg(10)); | ||
| } | ||
| } | ||
| else | ||
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Probably, you need to remove
EmitRet()declaration too since removed implementationThere was a problem hiding this comment.
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Good catch, will add to next PR.