[RISC-V] Implement some of the NYI methods in unwindriscv64

[sirntar]

This PR contains implementation for some of the NYI methods in unwindriscv64.

About Compiler::mapRegNumToDwarfReg:
I've mapped only basic and floating pointer registers as we are not supporting V-extension right now.

About GetUnwindSizeFromUnwindHeader:
I'm not 100% certain whether this is a correct implementation, so I would be grateful if someone can check it.

---

Part of #84834
cc @wscho77 @HJLeee @clamp03 @JongHeonChoi @t-mustafin @gbalykov @ashaurtaev @yurai007 @tomeksowi @Bajtazar

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Issue Details

---

This PR contains implementation for some of the NYI methods in unwindriscv64.

About Compiler::mapRegNumToDwarfReg:
I've mapped only basic and floating pointer registers as we are not supporting V-extension right now.

About GetUnwindSizeFromUnwindHeader:
I'm not 100% certain whether this is a correct implementation, so I would be grateful if someone can check it.

---

Part of #84834
cc @wscho77 @HJLeee @clamp03 @JongHeonChoi @t-mustafin @gbalykov @ashaurtaev @yurai007 @tomeksowi @Bajtazar

Author:	sirntar
Assignees:	-
Labels:	area-CodeGen-coreclr, community-contribution
Milestone:	-

[clamp03]

Noti: @shushanhf I checked dwarf register numbers for other archs as well as riscv. I think loongarch64 DWARF register number for floating-point register starts from 32 according to https://github.com/loongson/la-abi-specs/blob/release/ladwarf.adoc#loongarch-specific-dwarf-definitions. Please take a look. :)

runtime/src/coreclr/jit/unwindloongarch64.cpp

Lines 123 to 125 in 84087b4

	case REG_F0:
	dwarfReg = 64;
	break;

[sirntar]

Noti: @shushanhf I checked dwarf register numbers for other archs as well as riscv. I think loongarch64 DWARF register number for floating-point register starts from 32 according to https://github.com/loongson/la-abi-specs/blob/release/ladwarf.adoc#loongarch-specific-dwarf-definitions. Please take a look. :)

runtime/src/coreclr/jit/unwindloongarch64.cpp

Lines 123 to 125 in 84087b4

	case REG_F0:
	dwarfReg = 64;
	break;

I sent an email about it to @shushanhf last week. If I remember correctly, he responded that it could have been a part of SIMD functionality that hasn't been pushed to upstream. I also made a small fix for loongarch64 (sirntar@58edd0b), but since I don't have a loongarch64 platform to test it, I didn't create any pull request.

[clamp03]

I sent an email about it to @shushanhf last week. If I remember correctly, he responded that it could have been a part of SIMD functionality that hasn't been pushed to upstream. I also made a small fix for loongarch64 (sirntar@58edd0b), but since I don't have a loongarch64 platform to test it, I didn't create any pull request.

Ah. You already sent an email to him. I think he will handle it. :)

[shushanhf]

Noti: @shushanhf I checked dwarf register numbers for other archs as well as riscv. I think loongarch64 DWARF register number for floating-point register starts from 32 according to https://github.com/loongson/la-abi-specs/blob/release/ladwarf.adoc#loongarch-specific-dwarf-definitions. Please take a look. :)

runtime/src/coreclr/jit/unwindloongarch64.cpp

Lines 123 to 125 in 84087b4

	case REG_F0:
	dwarfReg = 64;
	break;

I sent an email about it to @shushanhf last week. If I remember correctly, he responded that it could have been a part of SIMD functionality that hasn't been pushed to upstream. I also made a small fix for loongarch64 (sirntar@58edd0b), but since I don't have a loongarch64 platform to test it, I didn't create any pull request.

Sorry, I forgot to reply to all.

Thanks very much!

I think that is for SIMD registers context. Although the main branch doesn't contain the LoongArch64-SIMD
In fact our local runtime had supported the LoongArch64-SIMD, of course the OS also supports the SIMD.