Add ARM64 encodings for group IF_SVE_GQ_3A #98352
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsAdds encodings for bfcvtnt, fcvtlt, fcvtnt and fcvtxnt. Contributing towards #94549.
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kunalspathak
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kunalspathak
requested changes
Feb 13, 2024
src/coreclr/jit/emitarm64.h
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| @@ -827,6 +827,10 @@ static insOpts optMakeArrangement(emitAttr datasize, emitAttr elemsize); | |||
| // For the given 'datasize' and 'opt' returns true if it specifies a valid vector register arrangement | |||
| static bool isValidArrangement(emitAttr datasize, insOpts opt); | |||
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| // Expands an option that has different size operands (INS_OPTS_*_TO_*) into a pair of scalable options where | |||
| // the first describes the size of the destination operand and the second describes the size of the source operand. | |||
| std::pair<insOpts, insOpts> optExpandConversionPair(insOpts opt); | |||
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we do not use standard libraries function like std::pair. Can you instead change it to something like
Suggested change
| std::pair<insOpts, insOpts> optExpandConversionPair(insOpts opt); | |
| void optExpandConversionPair(insOpts opt, insOpts& dst, insOpts& src); |
src/coreclr/jit/emitarm64.cpp
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| case INS_sve_fcvtnt: | ||
| if (id->idInsOpt() == INS_OPTS_S_TO_H) | ||
| { | ||
| code ^= (1 << 22 | 1 << 17); |
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can you instead change the below to:
runtime/src/coreclr/jit/instrsarm64sve.h
Line 1316 in eb0c20c
- INST2(fcvtnt, "fcvtnt", 0, IF_SVE_2BJ, 0x64CAA000, 0x650A3C00 )
- // FCVTNT <Zd>.S, <Pg>/M, <Zn>.D SVE_GQ_3A 0110010011001010 101gggnnnnnddddd 64CA A000
+ INST2(fcvtnt, "fcvtnt", 0, IF_SVE_2BJ, 0x6488A000, 0x650A3C00 )
+ // FCVTNT <Zd>.H, <Pg>/M, <Zn>.S SVE_GQ_3A 0110010010001000 101gggnnnnnddddd 6488 A000 and then use |:
Suggested change
| code ^= (1 << 22 | 1 << 17); | |
| code |= (1 << 22 | 1 << 17); |
src/coreclr/jit/emitarm64.cpp
Outdated
| case INS_sve_fcvtlt: | ||
| if (id->idInsOpt() == INS_OPTS_H_TO_S) | ||
| { | ||
| code ^= (1 << 22 | 1 << 17); |
src/coreclr/jit/emitarm64.cpp
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| case INS_sve_fcvtxnt: | ||
| case INS_sve_bfcvtnt: | ||
| assert(isVectorRegister(reg1)); // ddddd | ||
| assert(isPredicateRegister(reg2)); // ggg |
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Suggested change
| assert(isPredicateRegister(reg2)); // ggg | |
| assert(isLowPredicateRegister(reg2)); // ggg |
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and at other places too, the assert should be for LowPredicateRegister().
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@a74nh @kunalspathak @dotnet/arm64-contrib |
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Failures are known and superpmi-x64 is clean. |
Diff results for #98352Throughput diffsThroughput diffs for linux/arm64 ran on windows/x64MinOpts (-0.01% to +0.00%)
Throughput diffs for osx/arm64 ran on windows/x64MinOpts (-0.01% to +0.00%)
Throughput diffs for windows/arm64 ran on windows/x64MinOpts (-0.00% to +0.01%)
Details here |
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Adds encodings for bfcvtnt, fcvtlt, fcvtnt and fcvtxnt.
Contributing towards #94549.