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[ARM Decoding] Convert instruction immediates appear incorrect at 64 #241

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nathanhjay opened this issue Nov 15, 2016 · 1 comment
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[ARM Decoding] Convert instruction immediates appear incorrect at 64 #241

nathanhjay opened this issue Nov 15, 2016 · 1 comment
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ARM decoding cleanup

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@nathanhjay
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I think we may be causing the immediate to wrap around to zero because it's a 64 bit shift on a 64 bit register, but we shouldn't do that.

Bytes: 9f 0 59 9e
Output: fcvtzu xzr, d4, 0x0
Expected Output: fcvtzu xzr, d4, #64
ssunny7 added a commit that referenced this issue Dec 2, 2016
@ssunny7
Issue #241 ([ARM Decoding] Convert instruction immediates appear
d4c5b36 
	incorrect at 64)

Use different number of bits for size of 'fbits' operand in 32 vs 64 bit
modes of the scalar to fixed-point FP instructions.
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ssunny7 commented Dec 2, 2016

Fixed by d4c5b36.

@wrwilliams wrwilliams added the bug label Feb 9, 2017
@wrwilliams wrwilliams modified the milestone: ARM decoding cleanup Mar 14, 2017
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