add RISC-V support to UCC 1.2.0

[bedroge]

RISC-V support was added after the 1.2.0 release, but the patch file of the PR seems to work fine for 1.2.0 as well. As it's not officially supported, I'm only applying the patch on RISC-V build hosts.

[bedroge]

@boegelbot please test @ jsc-zen3

[bedroge]

Test report by @bedroge
SUCCESS
Build succeeded for 1 out of 1 (1 easyconfigs in total)
starfive - Linux Debian GNU/Linux n/a, RISC-V-64, UNKNOWN, Python 3.10.9
See https://gist.github.com/bedroge/f4aa44c779229cb7fca37a69200971aa for a full test report.

[boegelbot]

@bedroge: Request for testing this PR well received on jsczen3l1.int.jsc-zen3.fz-juelich.de

PR test command 'if [[ develop != 'develop' ]]; then EB_BRANCH=develop ./easybuild_develop.sh 2> /dev/null 1>&2; EB_PREFIX=/home/boegelbot/easybuild/develop source init_env_easybuild_develop.sh; fi; EB_PR=20432 EB_ARGS= EB_CONTAINER= EB_REPO=easybuild-easyconfigs EB_BRANCH=develop /opt/software/slurm/bin/sbatch --job-name test_PR_20432 --ntasks=8 ~/boegelbot/eb_from_pr_upload_jsc-zen3.sh' executed!

• exit code: 0
• output:

Submitted batch job 4041

Test results coming soon (I hope)...

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Message to humans: this is just bookkeeping information for me,
it is of no use to you (unless you think I have a bug, which I don't).

[boegelbot]

Test report by @boegelbot
SUCCESS
Build succeeded for 1 out of 1 (1 easyconfigs in total)
jsczen3c1.int.jsc-zen3.fz-juelich.de - Linux Rocky Linux 9.3, x86_64, AMD EPYC-Milan Processor (zen3), Python 3.9.18
See https://gist.github.com/boegelbot/0a347d8b2c958bf310028d99070d9d4a for a full test report.

[SebastianAchilles]

Test report by @SebastianAchilles
SUCCESS
Build succeeded for 1 out of 1 (1 easyconfigs in total)
arriesgado-2 - Linux Ubuntu 22.04, RISC-V-64, UNKNOWN (u74mc), Python 3.10.12
See https://gist.github.com/SebastianAchilles/af58ab018478d15d6d78b695f8fda84a for a full test report.

[SebastianAchilles]

lgtm

[SebastianAchilles]

lgtm

[SebastianAchilles]

Going in, thanks @bedroge!