Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"

This reverts commit b70c27c.
efabless · Apr 4, 2022 · f633b11 · f633b11
1 parent 8b9c4c8
commit f633b11
Show file tree

Hide file tree

Showing 2 changed files with 11 additions and 9 deletions.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
@@ -236,6 +236,7 @@ module caravel (
 		.vccd2_pad	(vccd2),		// User area 2 1.8V supply
 		.vssd1_pad	(vssd1),		// User area 1 digital ground
 		.vssd2_pad	(vssd2),		// User area 2 digital ground
+	`endif
 	// Core Side Pins
 	.vddio	(vddio_core),
 	.vssio	(vssio_core),
@@ -251,7 +252,6 @@ module caravel (
 	.vccd2	(vccd2_core),
 	.vssd1	(vssd1_core),
 	.vssd2	(vssd2_core),
-	`endif
 
 	.gpio(gpio),
 	.mprj_io(mprj_io),
@@ -1410,7 +1410,8 @@ module caravel (
 	`ifdef USE_POWER_PINS
 		.vdd3v3(vddio_core),
 		.vdd1v8(vccd_core),
-		.vss(vssio_core),
+		.vss3v3(vssio_core),
+		.vss1v8(vssd_core),
 	`endif
 		.porb_h(porb_h),
 		.porb_l(porb_l),

diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
@@ -20,7 +20,8 @@ module simple_por(
 `ifdef USE_POWER_PINS
     inout vdd3v3,
     inout vdd1v8,
-    inout vss,
+    inout vss3v3,
+    inout vss1v8,
 `endif
     output porb_h,
     output porb_l,
@@ -54,9 +55,9 @@ module simple_por(
     sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
 `ifdef USE_POWER_PINS
 	.VPWR(vdd3v3),
-	.VGND(vss),
+	.VGND(vss3v3),
 	.VPB(vdd3v3),
-	.VNB(vss),
+	.VNB(vss3v3),
 `endif
 	.A(inode),
 	.X(mid)
@@ -65,9 +66,9 @@ module simple_por(
     sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
 `ifdef USE_POWER_PINS
 	.VPWR(vdd3v3),
-	.VGND(vss),
+	.VGND(vss3v3),
 	.VPB(vdd3v3),
-	.VNB(vss),
+	.VNB(vss3v3),
 `endif
 	.A(mid),
 	.X(porb_h)
@@ -78,8 +79,8 @@ module simple_por(
 	.VPWR(vdd3v3),
 	.VPB(vdd3v3),
 	.LVPWR(vdd1v8),
-	.VNB(vss),
-	.VGND(vss),
+	.VNB(vss3v3),
+	.VGND(vss3v3),
 `endif
 	.A(porb_h),
 	.X(porb_l)