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Corrected the gpio_control_block to avoid potential floating signal driving an inverter #89

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merged 1 commit into from
Apr 25, 2022

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RTimothyEdwards
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Corrected the gpio_control_block so that the user_gpio_out signal
does not pass through an inverter, so that the input can remain
unconnected. Rewired the existing implementation to use an
alternative gate that has an inverting input so that the
user_gpio_out signal can be left undriven when the GPIOs are in
the management enable state. This is a simple logic refactoring
and does not change the logic function. The manual rewiring has
been confirmed by LVS, but at least one GL simulation should be
run to confirm that the logic function remains the same as before.

does not pass through an inverter, so that the input can remain
unconnected.  Rewired the existing implementation to use an
alternative gate that has an inverting input so that the
user_gpio_out signal can be left undriven when the GPIOs are in
the management enable state.  This is a simple logic refactoring
and does not change the logic function.  The manual rewiring has
been confirmed by LVS, but at least one GL simulation should be
run to confirm that the logic function remains the same as before.
@jeffdi jeffdi self-requested a review April 25, 2022 18:27
@jeffdi jeffdi merged commit b2089fe into main Apr 25, 2022
@jeffdi jeffdi deleted the gpio_user_out_fix branch April 25, 2022 18:27
antonblanchard pushed a commit to antonblanchard/caravel that referenced this pull request Apr 27, 2022
fix make <block> running all make blocks
M0stafaRady pushed a commit that referenced this pull request Sep 30, 2022
does not pass through an inverter, so that the input can remain
unconnected.  Rewired the existing implementation to use an
alternative gate that has an inverting input so that the
user_gpio_out signal can be left undriven when the GPIOs are in
the management enable state.  This is a simple logic refactoring
and does not change the logic function.  The manual rewiring has
been confirmed by LVS, but at least one GL simulation should be
run to confirm that the logic function remains the same as before.
@RTimothyEdwards RTimothyEdwards added error Something isn't working RTL Verilog source code changed PnR Gate level verilog and/or layout changed labels Oct 3, 2022
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