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use integer_array_t instead of array_t
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1138-4EB committed Nov 26, 2019
1 parent b13044a commit 9020d6e
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Showing 4 changed files with 86 additions and 71 deletions.
1 change: 0 additions & 1 deletion examples/vhdl/array/run.py
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,6 @@

vu = VUnit.from_argv()
vu.add_osvvm()
vu.add_array_util()

src_path = join(dirname(__file__), "src")

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116 changes: 68 additions & 48 deletions examples/vhdl/array/src/test/tb_sobel_x.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -10,78 +10,92 @@ use ieee.numeric_std.all;

library vunit_lib;
context vunit_lib.vunit_context;
use vunit_lib.array_pkg.all;


library osvvm;
use osvvm.RandomPkg.all;
use osvvm.RandomPkg.RandomPType;

entity tb_sobel_x is
generic (
runner_cfg : string;
tb_path : string);
tb_path : string
);
end entity;

architecture tb of tb_sobel_x is
signal clk : std_logic := '0';
signal input_tvalid : std_logic := '0';
signal input_tlast : std_logic := '0';
signal input_tdata : unsigned(14-1 downto 0) := (others => '0');

signal clk : std_logic := '0';
signal input_tvalid : std_logic := '0';
signal input_tlast : std_logic := '0';
signal input_tdata : unsigned(13 downto 0) := (others => '0');
signal output_tvalid : std_logic;
signal output_tlast : std_logic;
signal output_tdata : signed(input_tdata'length downto 0);
signal output_tlast : std_logic;
signal output_tdata : signed(input_tdata'length downto 0);

shared variable image : array_t;
shared variable reference_image : array_t;
signal image, reference_image : integer_array_t;

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@kraigher

kraigher Nov 26, 2019

You can just use a shared variable. It works in all simulators even if is not part of the VHDL-standard

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@eine

eine Nov 26, 2019

Owner

GHDL does not, by default:

=== Command output: ===
/src/examples/vhdl/array/src/test/tb_sobel_x.vhd:34:19: type of a shared variable must be a protected type
/src/examples/vhdl/array/src/test/tb_sobel_x.vhd:34:26: type of a shared variable must be a protected type
/src/examples/vhdl/array/src/test/tb_sobel_x.vhd:41:16:warning: declaration of "image" hides variable "image" [-Whide]
/usr/local/bin/ghdl: compilation error

Compile failed

It works if I set:

vu.set_compile_option("ghdl.flags", ["-frelaxed"])
vu.set_sim_option("ghdl.elab_flags", ["-frelaxed"])

Should we go this way?
signal start, data_check_done, stimuli_done : boolean := false;

begin

main : process
procedure sobel_x(variable image : inout array_t;
variable result : inout array_t) is
begin
result.init_2d(width => image.width,
height => image.height,
bit_width => image.bit_width+1,
is_signed => true);
procedure sobel_x(
signal image : inout integer_array_t;
signal result : inout integer_array_t
) is begin
result <= new_2d(
width => image.width,
height => image.height,
bit_width => image.bit_width+1,
is_signed => true
);

for y in 0 to image.height-1 loop
for x in 0 to image.width-1 loop
result.set(x => x, y => y,
value => (image.get(minimum(x+1, image.width-1),y) -
image.get(maximum(x-1, 0), y)));
set(
result,
x => x,
y => y,
value => (
get(image, minimum(x+1, image.width-1),y)
- get(image, maximum(x-1, 0), y)
)
);
end loop;
end loop;

end procedure;

variable rnd : RandomPType;

procedure randomize(variable arr : inout array_t) is
begin
for idx in 0 to arr.length-1 loop
arr.set(idx, value => rnd.RandInt(arr.lower_limit, arr.upper_limit));
end loop;
end procedure;

procedure run_test is
begin
wait until rising_edge(clk);
start <= true;
wait until rising_edge(clk);
start <= false;

wait until (stimuli_done and
data_check_done and
rising_edge(clk));
wait until (
stimuli_done and
data_check_done and
rising_edge(clk)
);
end procedure;

procedure test_random_image(width, height : natural) is
begin
image.init_2d(width => width, height => height,
bit_width => input_tdata'length,
is_signed => false);
randomize(image);
image <= new_2d(
width => width, height => height,
bit_width => input_tdata'length,
is_signed => false
);

for idx in 0 to image.length-1 loop
set(
image,
idx,
value => rnd.RandInt(image.lower_limit, image.upper_limit)
);
end loop;

sobel_x(image, result => reference_image);
run_test;
end procedure;
Expand All @@ -96,8 +110,8 @@ begin
test_random_image(16, 1);
test_random_image(1, 1);
elsif run("test_input_file_against_output_file") then
image.load_csv(tb_path & "input.csv");
reference_image.load_csv(tb_path & "output.csv");
image <= load_csv(tb_path & "input.csv");
reference_image <= load_csv(tb_path & "output.csv");
run_test;
end if;
end loop;
Expand All @@ -110,9 +124,11 @@ begin
wait until start and rising_edge(clk);
stimuli_done <= false;

report ("Sending image of size " &
to_string(image.width) & "x" &
to_string(image.height));
report (
"Sending image of size " &
to_string(image.width) & "x" &
to_string(image.height)
);

for y in 0 to image.height-1 loop
for x in 0 to image.width-1 loop
Expand All @@ -123,7 +139,7 @@ begin
else
input_tlast <= '0';
end if;
input_tdata <= to_unsigned(image.get(x,y), input_tdata'length);
input_tdata <= to_unsigned(get(image, x, y), input_tdata'length);
end loop;
end loop;

Expand All @@ -141,28 +157,32 @@ begin
for x in 0 to reference_image.width-1 loop
wait until output_tvalid = '1' and rising_edge(clk);
check_equal(output_tlast, x = reference_image.width-1);
check_equal(output_tdata, reference_image.get(x, y),
check_equal(output_tdata, get(reference_image, x, y),
"x=" & to_string(x) & " y=" & to_string(y));
end loop;
end loop;
report ("Done checking image of size " &
to_string(reference_image.width) & "x" &
to_string(reference_image.height));
report (
"Done checking image of size " &
to_string(reference_image.width) & "x" &
to_string(reference_image.height)
);
data_check_done <= true;
end process;

clk <= not clk after 1 ns;

dut : entity work.sobel_x
generic map (
data_width => input_tdata'length)
data_width => input_tdata'length
)
port map (
clk => clk,
input_tvalid => input_tvalid,
input_tlast => input_tlast,
input_tdata => input_tdata,
output_tvalid => output_tvalid,
output_tlast => output_tlast,
output_tdata => output_tdata);
output_tdata => output_tdata
);

end architecture;
10 changes: 3 additions & 7 deletions examples/vhdl/array_axis_vcs/run.py
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Expand Up @@ -8,11 +8,9 @@
Array and AXI4 Stream Verification Components
---------------------------------------------
Demonstrates ``array_t``, ``axi_stream_master_t`` and ``axi_stream_slave_t``
data types of ``array_pkg.vhd``, ``stream_master_pkg`` and ``stream_slave_pkg``,
respectively. Also, ``push_axi_stream`` of ``axi_stream_pkg`` is used. A CSV file
is read, the content is sent in a row-major order to an AXI Stream buffer (FIFO)
and it is received back to be saved in a different file. Further information can
Shows how to use ``integer_array_t``, ``axi_stream_master_t`` and ``axi_stream_slave_t``.
A CSV file is read, the content is sent in a row-major order to an AXI Stream buffer
(FIFO) and it is received back to be saved in a different file. Further information can
be found in the :ref:`verification component library user guide <vc_library>`,
in subsection :ref:`Stream <stream_vci>` and in
:vunit_file:`vhdl/verification_components/test/tb_axi_stream.vhd <vunit/vhdl/verification_components/test/tb_axi_stream.vhd>`.
Expand All @@ -23,8 +21,6 @@

vu = VUnit.from_argv()

vu.add_osvvm()
vu.add_array_util()
vu.add_verification_components()

src_path = join(dirname(__file__), "src")
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30 changes: 15 additions & 15 deletions examples/vhdl/array_axis_vcs/src/test/tb_axis_loop.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,6 @@ context ieee.ieee_std_context;
library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;
use vunit_lib.array_pkg.all;

entity tb_axis_loop is
generic (
Expand All @@ -32,13 +31,13 @@ architecture tb of tb_axis_loop is

-- Simulation constants

constant clk_period : time := 20 ns;
constant clk_period : time := 20 ns;
constant data_width : natural := 32;

-- AXI4Stream Verification Components

constant master_axi_stream : axi_stream_master_t := new_axi_stream_master(data_length => data_width);
constant slave_axi_stream : axi_stream_slave_t := new_axi_stream_slave(data_length => data_width);
constant slave_axi_stream : axi_stream_slave_t := new_axi_stream_slave(data_length => data_width);

-- Signals to/from the UUT from/to the verification components

Expand All @@ -48,7 +47,8 @@ architecture tb of tb_axis_loop is
-- tb signals and variables

signal clk, rst, rstn : std_logic := '0';
shared variable m_I, m_O : array_t;
constant m_I : integer_array_t := load_csv(tb_path & csv_i);
constant m_O : integer_array_t := new_2d(m_I.width, m_I.height, data_width, true);
signal start, done, saved : boolean := false;

begin
Expand Down Expand Up @@ -85,15 +85,13 @@ begin
done <= false;
wait until rising_edge(clk);

m_I.load_csv(tb_path & csv_i);

info("Sending m_I of size " & to_string(m_I.height) & "x" & to_string(m_I.width) & " to UUT...");

for y in 0 to m_I.height-1 loop
for x in 0 to m_I.width-1 loop
wait until rising_edge(clk);
if x = m_I.width-1 then last := '1'; else last := '0'; end if;
push_axi_stream(net, master_axi_stream, std_logic_vector(to_signed(m_I.get(x,y), data_width)) , tlast => last);
push_axi_stream(net, master_axi_stream, std_logic_vector(to_signed(get(m_I, x, y), data_width)) , tlast => last);
end loop;
end loop;

Expand All @@ -111,8 +109,6 @@ begin
saved <= false;
wait for 50*clk_period;

m_O.init_2d(m_I.width, m_I.height, o'length, true);

info("Receiving m_O of size " & to_string(m_O.height) & "x" & to_string(m_O.width) & " from UUT...");

for y in 0 to m_O.height-1 loop
Expand All @@ -121,14 +117,14 @@ begin
if (x = m_O.width-1) and (last='0') then
error("Something went wrong. Last misaligned!");
end if;
m_O.set(x,y,to_integer(signed(o)));
set(m_O, x, y, to_integer(signed(o)));
end loop;
end loop;

info("m_O read!");

wait until rising_edge(clk);
m_O.save_csv(tb_path & csv_o);
save_csv(m_O, tb_path & csv_o);

info("m_O saved!");

Expand All @@ -140,23 +136,27 @@ begin

vunit_axism: entity vunit_lib.axi_stream_master
generic map (
master => master_axi_stream)
master => master_axi_stream
)
port map (
aclk => clk,
tvalid => m_valid,
tready => m_ready,
tdata => m_data,
tlast => m_last);
tlast => m_last
);

vunit_axiss: entity vunit_lib.axi_stream_slave
generic map (
slave => slave_axi_stream)
slave => slave_axi_stream
)
port map (
aclk => clk,
tvalid => s_valid,
tready => s_ready,
tdata => s_data,
tlast => s_last);
tlast => s_last
);

--

Expand Down

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