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Generated from stm32-data fff3cddff0b1ff33149e479e8fbbe358c3de6d38
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Embassy CI committed Apr 5, 2024
1 parent 142bd89 commit 1daa54f
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Showing 18 changed files with 385 additions and 445 deletions.
2 changes: 1 addition & 1 deletion data/registers/crc_v2.json
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
"description": "Cyclic Redundancy Check calculation unit",
"items": [
{
"name": "DR",
"name": "DR32",
"description": "Data register",
"byte_offset": 0
},
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2 changes: 1 addition & 1 deletion data/registers/crc_v3.json
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
"description": "Cyclic Redundancy Check calculation unit",
"items": [
{
"name": "DR",
"name": "DR32",
"description": "Data register",
"byte_offset": 0
},
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23 changes: 9 additions & 14 deletions data/registers/spi_v2.json
Original file line number Diff line number Diff line change
Expand Up @@ -21,10 +21,16 @@
"fieldset": "SR"
},
{
"name": "DR",
"description": "data register",
"name": "DR16",
"description": "data register - half-word sized",
"byte_offset": 12,
"fieldset": "DR"
"bit_size": 16
},
{
"name": "DR8",
"description": "data register - byte sized",
"byte_offset": 12,
"bit_size": 8
},
{
"name": "CRCPR",
Expand Down Expand Up @@ -252,17 +258,6 @@
}
]
},
"fieldset/DR": {
"description": "data register",
"fields": [
{
"name": "DR",
"description": "Data register",
"bit_offset": 0,
"bit_size": 16
}
]
},
"fieldset/I2SCFGR": {
"description": "I2S configuration register",
"fields": [
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56 changes: 30 additions & 26 deletions data/registers/spi_v3.json
Original file line number Diff line number Diff line change
Expand Up @@ -47,18 +47,44 @@
"fieldset": "IFCR"
},
{
"name": "TXDR",
"name": "TXDR32",
"description": "Transmit Data Register",
"byte_offset": 32,
"access": "Write"
},
{
"name": "TXDR16",
"description": "Transmit Data Register - half-word sized",
"byte_offset": 32,
"access": "Write",
"bit_size": 16
},
{
"name": "TXDR8",
"description": "Transmit Data Register - byte sized",
"byte_offset": 32,
"access": "Write",
"fieldset": "TXDR"
"bit_size": 8
},
{
"name": "RXDR",
"name": "RXDR32",
"description": "Receive Data Register",
"byte_offset": 48,
"access": "Read"
},
{
"name": "RXDR16",
"description": "Receive Data Register - half-word sized",
"byte_offset": 48,
"access": "Read",
"bit_size": 16
},
{
"name": "RXDR8",
"description": "Receive Data Register - byte sized",
"byte_offset": 48,
"access": "Read",
"fieldset": "RXDR"
"bit_size": 8
},
{
"name": "CRCPOLY",
Expand Down Expand Up @@ -483,17 +509,6 @@
}
]
},
"fieldset/RXDR": {
"description": "Receive Data Register",
"fields": [
{
"name": "RXDR",
"description": "Receive data register",
"bit_offset": 0,
"bit_size": 32
}
]
},
"fieldset/SR": {
"description": "Status Register",
"fields": [
Expand Down Expand Up @@ -608,17 +623,6 @@
}
]
},
"fieldset/TXDR": {
"description": "Transmit Data Register",
"fields": [
{
"name": "TXDR",
"description": "Transmit data register",
"bit_offset": 0,
"bit_size": 32
}
]
},
"fieldset/UDRDR": {
"description": "Underrun Data Register",
"fields": [
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56 changes: 30 additions & 26 deletions data/registers/spi_v4.json
Original file line number Diff line number Diff line change
Expand Up @@ -47,18 +47,44 @@
"fieldset": "IFCR"
},
{
"name": "TXDR",
"name": "TXDR32",
"description": "Transmit Data Register",
"byte_offset": 32,
"access": "Write"
},
{
"name": "TXDR16",
"description": "Transmit Data Register - half-word sized",
"byte_offset": 32,
"access": "Write",
"bit_size": 16
},
{
"name": "TXDR8",
"description": "Transmit Data Register - byte sized",
"byte_offset": 32,
"access": "Write",
"fieldset": "TXDR"
"bit_size": 8
},
{
"name": "RXDR",
"name": "RXDR32",
"description": "Receive Data Register",
"byte_offset": 48,
"access": "Read"
},
{
"name": "RXDR16",
"description": "Receive Data Register - half-word sized",
"byte_offset": 48,
"access": "Read",
"bit_size": 16
},
{
"name": "RXDR8",
"description": "Receive Data Register - byte sized",
"byte_offset": 48,
"access": "Read",
"fieldset": "RXDR"
"bit_size": 8
},
{
"name": "CRCPOLY",
Expand Down Expand Up @@ -478,17 +504,6 @@
}
]
},
"fieldset/RXDR": {
"description": "Receive Data Register",
"fields": [
{
"name": "RXDR",
"description": "Receive data register",
"bit_offset": 0,
"bit_size": 32
}
]
},
"fieldset/SR": {
"description": "Status Register",
"fields": [
Expand Down Expand Up @@ -597,17 +612,6 @@
}
]
},
"fieldset/TXDR": {
"description": "Transmit Data Register",
"fields": [
{
"name": "TXDR",
"description": "Transmit data register",
"bit_offset": 0,
"bit_size": 32
}
]
},
"fieldset/UDRDR": {
"description": "Underrun Data Register",
"fields": [
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56 changes: 30 additions & 26 deletions data/registers/spi_v5.json
Original file line number Diff line number Diff line change
Expand Up @@ -52,18 +52,44 @@
"fieldset": "AUTOCR"
},
{
"name": "TXDR",
"name": "TXDR32",
"description": "Transmit Data Register",
"byte_offset": 32,
"access": "Write"
},
{
"name": "TXDR16",
"description": "Transmit Data Register - half-word sized",
"byte_offset": 32,
"access": "Write",
"bit_size": 16
},
{
"name": "TXDR8",
"description": "Transmit Data Register - byte sized",
"byte_offset": 32,
"access": "Write",
"fieldset": "TXDR"
"bit_size": 8
},
{
"name": "RXDR",
"name": "RXDR32",
"description": "Receive Data Register",
"byte_offset": 48,
"access": "Read"
},
{
"name": "RXDR16",
"description": "Receive Data Register - half-word sized",
"byte_offset": 48,
"access": "Read",
"bit_size": 16
},
{
"name": "RXDR8",
"description": "Receive Data Register - byte sized",
"byte_offset": 48,
"access": "Read",
"fieldset": "RXDR"
"bit_size": 8
},
{
"name": "CRCPOLY",
Expand Down Expand Up @@ -506,17 +532,6 @@
}
]
},
"fieldset/RXDR": {
"description": "Receive Data Register",
"fields": [
{
"name": "RXDR",
"description": "Receive data register",
"bit_offset": 0,
"bit_size": 32
}
]
},
"fieldset/SR": {
"description": "Status Register",
"fields": [
Expand Down Expand Up @@ -625,17 +640,6 @@
}
]
},
"fieldset/TXDR": {
"description": "Transmit Data Register",
"fields": [
{
"name": "TXDR",
"description": "Transmit data register",
"bit_offset": 0,
"bit_size": 32
}
]
},
"fieldset/UDRDR": {
"description": "Underrun Data Register",
"fields": [
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8 changes: 4 additions & 4 deletions stm32-metapac/src/peripherals/crc_v2.rs
Original file line number Diff line number Diff line change
Expand Up @@ -19,14 +19,14 @@ impl Crc {
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "Data register"]
#[doc = "Data register - half-word sized"]
#[inline(always)]
pub const fn dr(self) -> crate::common::Reg<u32, crate::common::RW> {
pub const fn dr16(self) -> crate::common::Reg<u16, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "Data register - half-word sized"]
#[doc = "Data register"]
#[inline(always)]
pub const fn dr16(self) -> crate::common::Reg<u16, crate::common::RW> {
pub const fn dr32(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "Data register - byte sized"]
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8 changes: 4 additions & 4 deletions stm32-metapac/src/peripherals/crc_v3.rs
Original file line number Diff line number Diff line change
Expand Up @@ -19,14 +19,14 @@ impl Crc {
pub const fn as_ptr(&self) -> *mut () {
self.ptr as _
}
#[doc = "Data register"]
#[doc = "Data register - half-word sized"]
#[inline(always)]
pub const fn dr(self) -> crate::common::Reg<u32, crate::common::RW> {
pub const fn dr16(self) -> crate::common::Reg<u16, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "Data register - half-word sized"]
#[doc = "Data register"]
#[inline(always)]
pub const fn dr16(self) -> crate::common::Reg<u16, crate::common::RW> {
pub const fn dr32(self) -> crate::common::Reg<u32, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0usize) as _) }
}
#[doc = "Data register - byte sized"]
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32 changes: 7 additions & 25 deletions stm32-metapac/src/peripherals/spi_v2.rs
Original file line number Diff line number Diff line change
Expand Up @@ -34,9 +34,14 @@ impl Spi {
pub const fn sr(self) -> crate::common::Reg<regs::Sr, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x08usize) as _) }
}
#[doc = "data register"]
#[doc = "data register - half-word sized"]
#[inline(always)]
pub const fn dr(self) -> crate::common::Reg<regs::Dr, crate::common::RW> {
pub const fn dr16(self) -> crate::common::Reg<u16, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "data register - byte sized"]
#[inline(always)]
pub const fn dr8(self) -> crate::common::Reg<u8, crate::common::RW> {
unsafe { crate::common::Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
}
#[doc = "CRC polynomial register"]
Expand Down Expand Up @@ -399,29 +404,6 @@ pub mod regs {
Crcpr(0)
}
}
#[doc = "data register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
pub struct Dr(pub u32);
impl Dr {
#[doc = "Data register"]
#[inline(always)]
pub const fn dr(&self) -> u16 {
let val = (self.0 >> 0usize) & 0xffff;
val as u16
}
#[doc = "Data register"]
#[inline(always)]
pub fn set_dr(&mut self, val: u16) {
self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
}
}
impl Default for Dr {
#[inline(always)]
fn default() -> Dr {
Dr(0)
}
}
#[doc = "I2S configuration register"]
#[repr(transparent)]
#[derive(Copy, Clone, Eq, PartialEq)]
Expand Down
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