Add support for the CV32E40P RISC-V CPU

[piotr-binkowski]

This PR adds a CV32E40P RISC-V CPU. It was tested on an Arty board target with lower clock frequency (core has timing issues on 100MHz but works fine at 50MHz):

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on May 20 2020 12:49:52
 BIOS CRC passed (791d5d2b)

 Migen git sha1: b1b2b29
 LiteX git sha1: b49055d5

--=============== SoC ==================--
CPU:       CV32E40P @ 50MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  262144KB

--========== Initialization ============--
Initializing SDRAM...
SDRAM now under software control
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |00000000000000000000000000000000| delays: -
m0, b02: |00000000000000000000000000000000| delays: -
m0, b03: |00000000000000000000000000000000| delays: -
m0, b04: |00000000000000000000000000000000| delays: -
m0, b05: |00000000000000000000000000000000| delays: -
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
m0, b08: |00000000000000000000000000000000| delays: -
m0, b09: |00000000000000000000000000000000| delays: -
m0, b10: |00000000000000000000000000000000| delays: -
m0, b11: |00000000000000000000000000000000| delays: -
m0, b12: |11111111111111111111111111100000| delays: 13+-13
m0, b13: |00000000000000000000000000000011| delays: 31+-01
m0, b14: |00000000000000000000000000000000| delays: -
m0, b15: |00000000000000000000000000000000| delays: -
best: m0, b12 delays: 13+-13
m1, b00: |00000000000000000000000000000000| delays: -
m1, b01: |00000000000000000000000000000000| delays: -
m1, b02: |00000000000000000000000000000000| delays: -
m1, b03: |00000000000000000000000000000000| delays: -
m1, b04: |00000000000000000000000000000000| delays: -
m1, b05: |00000000000000000000000000000000| delays: -
m1, b06: |00000000000000000000000000000000| delays: -
m1, b07: |00000000000000000000000000000000| delays: -
m1, b08: |00000000000000000000000000000000| delays: -
m1, b09: |00000000000000000000000000000000| delays: -
m1, b10: |00000000000000000000000000000000| delays: -
m1, b11: |00000000000000000000000000000000| delays: -
m1, b12: |11111111111111111111111111000000| delays: 13+-13
m1, b13: |00000000000000000000000000001111| delays: 30+-02
m1, b14: |00000000000000000000000000000000| delays: -
m1, b15: |00000000000000000000000000000000| delays: -
best: m1, b12 delays: 13+-13
SDRAM now under hardware control
Memtest OK
Memspeed Writes: 49Mbps Reads: 65Mbps

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>

Since now files used by the CPUs are stored in pythondata-cpu-* repositories, what are other needed steps to include this in LiteX?
PR to https://github.com/litex-hub/pythondata-auto adding a new entry for it in modules.ini?
(I did initial tests with https://github.com/antmicro/pythondata-cpu-cv32e40p but that probably should be regenerated using mainline pythondata-auto and placed in litex-hub after merging that PR)

[mithro]

@piotr-binkowski Please send a pull request to pythondata-auto repo.

[mithro]

I created https://github.com/litex-hub/pythondata-cpu-cv32e40p

[enjoy-digital]

@piotr-binkowski: Great, i'll review it soon.

[enjoy-digital]

Thanks for your work, this is clean and easy to review/understand, we can merge it.