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Feedback Contribution Support
Feedback, contributions greatly help improving open-source projects and any contribution to LiteX is welcome:
- You create a design with LiteX, it works and you are happy with it? Please let us know, we could list it as a useful resource! It could be used as an example and help other users.
- You try to use LiteX but it does not work, we could certainly help if you create an issue, but please have a look at the list of things we'll need to know to be able to help you.
- You've seen things that could be improved or have some ideas you think would be useful for the project? Please share it with us. If you don't feel confident enough to modify the code yourself, feel free to create an issue describing your idea(s) and describe how it could improve the project. If you think you are able to do the modification yourself, feel free to try and create a Pull Request. Even if this is not perfect, this would be welcomed and we will help you understand how you could eventually improve it or could do the modification for you.
- etc..
It's also possible you will think of things we would never have figured out ourselves or things you are expert in and would implement better than us and that's what we think make open-source so rewarding: everyone learn from each other!
We think LiteX could be useful and offer some innovative solutions for some projects, but we are also aware it's not perfect and/or will not be the solution for everyone/every project. If you are interested by the project and want to contribute, please do!, if the only thing that works for you with LiteX is making you angry, we're not sure the right project is for you :) (but are open to constructive criticism).
Please just feel free to create an issue to share your idea with us, if you also have ideas on the implementation, we encourage you to try it (that's how you'll learn and progress!) and submit it in the issue or even in a PR. LiteX community is very welcoming and we could give you directions/advices to implement your idea or do the implementation ourselves if that's something interesting for the whole project.
LiteX provides tutorials, examples of projects and default platforms/targets for very various FPGA boards. These ones have been tested/validated and most of them covered by our CI.
Since LiteX possibilities are infinite, it's not possible for us to support or test all combinations. The codebase can have some wanted limitations (because we don't have a need for this yet and haven't implemented this combination) or issues that are not. FPGA are also constraints in size/speed and constraints can also come from there. We are happy to have your feedback on eventual issues/limitations you could have identified, but please consider that analyzing, fixing it or adding support new features requires a minimum amount of information and time, so if you want us to take time to look at the issue, please also take a bit of your time to prepare the issue, "it does not work" is not enough :) Quite often the solution to complex issues is in small details, having enough information from the start could avoid quite some back and forth in the communication and save days!
If you are testing some example code with specific parameters that you think should be supported, please share with us (if you think that's relevant):
- Your test environment.
- The target/example you are building.
- The specific parameters you eventually added.
- The logs LiteX generate (during the build, on the console, from the toolchains).
- The timing report of your design.
If you are testing a design you created with the tools or developing a new feature and have troubles, in addition to the previous information, the best is generally to create a minimal reproduction of the issue and share it with us. This allows us to reproduce the issue and have all the information we need to investigate without having to ask you each time we progress.
Reading this is the first thing we'll ask you if your issue does not provide enough information, so you please try to anticipate :)
If you have an idea and think you can implement it, please go ahead, that's how you'll learn and progress! We encourage you to do so and will always welcome contributions, we can help to make sure it can be merged if useful for the whole project. If before doing the hard work you have doubts it will be possible to merge your work since maybe not useful for the whole project or too specific, please feel free to first create an issue to discuss this.
LiteX does not have strict coding rules, please just try (if possible) to a use coding style close to the already existing files.
While LiteX is an open-source project and we are really enjoying working on it, the team doing the development/maintenance is still small and often have others obligations since the initial goal of LiteX was to create custom FPGA based systems with it, so please understand if we need a few days to respond. The community is also growing and helping and a dedicated freenode channel can be found at #litex at irc.libera.chat.
We have the chance to have clients trusting us and funding systems built with LiteX or new developments but please consider that most of us can only answer you on working days and also need to spend weekend/holidays with our family and friends to come back with fresh minds and ideas!
We are happy to provide basic support for everyone, if you are developing a product, want to reuse LiteX or part of it (some of the cores, the infrastructure, etc...) and want extensive support or want us to customize things for you, please get in touch with us, seeing our work used on real products it what motivate us and we'll see together what we and our partners could do!
Have a question or want to get in touch? Our IRC channel is #litex at irc.libera.chat.
- Welcome to LiteX
- LiteX's internals
- How to
- Create a minimal SoC-TODO
- Add a new Board-TODO
- Add a new Core-WIP
- Add a new CPU-WIP
- Reuse-a-(System)Verilog,-VHDL,-Amaranth,-Spinal-HDL,-Chisel-core
- Use LiteX on the Acorn CLE 215+
- Load application code the CPU(s)
- Use Host Bridges to control/debug a SoC
- Use LiteScope to debug a SoC
- JTAG/GDB Debugging with VexRiscv CPU
- JTAG/GDB Debugging with VexRiscv-SMP, NaxRiscv and VexiiRiscv CPUs
- Document a SoC
- How to (Advanced)