add cv32e40px (#353)

core-v-mini-mcu.core

@@ -14,6 +14,7 @@ filesets:
     - openhwgroup.org:ip:cv32e40p
     - openhwgroup.org:ip:cv32e40x
     - openhwgroup.org:ip:cve2
+    - esl_epfl:ip:cv32e40px
     - pulp-platform.org:ip:gpio
     - pulp-platform.org::common_cells
     - pulp-platform.org::cluster_interconnect

hw/core-v-mini-mcu/cpu_subsystem.sv

@@ -265,6 +265,87 @@ module cpu_subsystem
     assign irq_ack_o = '0;
     assign irq_id_o  = '0;
 
+  end else if (CPU_TYPE == cv32e40px) begin : gen_cv32e40px
+
+    import cv32e40px_core_v_xif_pkg::*;
+
+    // instantiate the core
+    cv32e40px_top #(
+        .COREV_X_IF      (X_EXT),
+        .COREV_PULP      (COREV_PULP),
+        .COREV_CLUSTER   (0),
+        .FPU             (FPU),
+        .ZFINX           (ZFINX),
+        .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS)
+    ) cv32e40px_top_i (
+        .clk_i (clk_i),
+        .rst_ni(rst_ni),
+
+        .pulp_clock_en_i(1'b1),
+        .scan_cg_en_i   (1'b0),
+
+        .boot_addr_i        (BOOT_ADDR),
+        .mtvec_addr_i       (32'h0),
+        .dm_halt_addr_i     (DM_HALTADDRESS),
+        .hart_id_i          (32'h0),
+        .dm_exception_addr_i(32'h0),
+
+        .instr_addr_o  (core_instr_req_o.addr),
+        .instr_req_o   (core_instr_req_o.req),
+        .instr_rdata_i (core_instr_resp_i.rdata),
+        .instr_gnt_i   (core_instr_resp_i.gnt),
+        .instr_rvalid_i(core_instr_resp_i.rvalid),
+
+        .data_addr_o  (core_data_req_o.addr),
+        .data_wdata_o (core_data_req_o.wdata),
+        .data_we_o    (core_data_req_o.we),
+        .data_req_o   (core_data_req_o.req),
+        .data_be_o    (core_data_req_o.be),
+        .data_rdata_i (core_data_resp_i.rdata),
+        .data_gnt_i   (core_data_resp_i.gnt),
+        .data_rvalid_i(core_data_resp_i.rvalid),
+
+        // CORE-V-XIF
+        // Compressed interface
+        .x_compressed_valid_o(),
+        .x_compressed_ready_i(),
+        .x_compressed_req_o(),
+        .x_compressed_resp_i('0),
+        // Issue Interface
+        .x_issue_valid_o(),
+        .x_issue_ready_i(),
+        .x_issue_req_o(),
+        .x_issue_resp_i('0),
+        // Commit Interface
+        .x_commit_valid_o(),
+        .x_commit_o(),
+        // Memory request/response Interface
+        .x_mem_valid_i(),
+        .x_mem_ready_o(),
+        .x_mem_req_i('0),
+        .x_mem_resp_o(),
+        // Memory Result Interface
+        .x_mem_result_valid_o(),
+        .x_mem_result_o(),
+        // Result Interface
+        .x_result_valid_i(),
+        .x_result_ready_o(),
+        .x_result_i('0),
+
+        .irq_i    (irq_i),
+        .irq_ack_o(irq_ack_o),
+        .irq_id_o (irq_id_o),
+
+        .debug_req_i      (debug_req_i),
+        .debug_havereset_o(),
+        .debug_running_o  (),
+        .debug_halted_o   (),
+
+        .fetch_enable_i(fetch_enable),
+        .core_sleep_o
+
+    );
+
   end else begin : gen_cv32e40p
 
     // instantiate the core

hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl

@@ -20,7 +20,8 @@ package core_v_mini_mcu_pkg;
   typedef enum logic [1:0] {
     cv32e40p,
     cv32e20,
-    cv32e40x
+    cv32e40x,
+    cv32e40px
   } cpu_type_e;
 
   localparam cpu_type_e CpuType = ${cpu_type};

hw/vendor/esl_epfl_cv32e40px.core

@@ -0,0 +1,62 @@
+CAPI=2:
+
+# Copyright 2023 EPFL
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+name: "esl_epfl:ip:cv32e40px"
+description: "OpenHW Group RISC-V Core CV32E40Px"
+
+filesets:
+  files_rtl:
+    depend:
+    - pulp-platform.org::fpnew
+    files:
+    - esl_epfl_cv32e40px/rtl/include/cv32e40px_apu_core_pkg.sv
+    - esl_epfl_cv32e40px/rtl/include/cv32e40px_fpu_pkg.sv
+    - esl_epfl_cv32e40px/rtl/include/cv32e40px_pkg.sv
+    - esl_epfl_cv32e40px/rtl/include/cv32e40px_core_v_xif_pkg.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_alu.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_alu_div.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_ff_one.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_popcnt.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_compressed_decoder.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_controller.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_cs_registers.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_decoder.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_int_controller.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_ex_stage.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_hwloop_regs.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_id_stage.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_if_stage.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_load_store_unit.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_mult.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_prefetch_buffer.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_prefetch_controller.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_obi_interface.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_aligner.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_sleep_unit.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_core.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_apu_disp.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_fifo.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_fp_wrapper.sv
+    - esl_epfl_cv32e40px/rtl/cv32e40px_top.sv
+    file_type: systemVerilogSource
+
+
+  files_clk_gate:
+    files:
+    - esl_epfl_cv32e40px/bhv/cv32e40px_sim_clock_gate.sv
+    file_type: systemVerilogSource
+
+  ff_regfile:
+    files:
+    - esl_epfl_cv32e40px/rtl/cv32e40px_register_file_ff.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+    - files_rtl
+    - ff_regfile
+    - target_sim? (files_clk_gate)

hw/vendor/esl_epfl_cv32e40px.lock.hjson

@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+  upstream:
+  {
+    url: https://github.com/esl-epfl/cv32e40px.git
+    rev: bfb6b76b19e036ade7265eb78ac15b733f0d758a
+  }
+}

hw/vendor/esl_epfl_cv32e40px.vendor.hjson

@@ -0,0 +1,27 @@
+// Copyright 2023 EPFL
+// Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+{
+  name: "esl_epfl_cv32e40px",
+  target_dir: "esl_epfl_cv32e40px",
+
+  upstream: {
+    url: "https://github.com/esl-epfl/cv32e40px.git",
+    rev: "bfb6b76b19e036ade7265eb78ac15b733f0d758a",
+  },
+
+  patch_dir: "patches/esl_epfl_cv32e40px",
+
+  exclude_from_upstream: [
+    "ci",
+    ".github",
+    "example_tb",
+    "CONTRIBUTING.md",
+    "Bender.yml",
+    ".gitlab-ci.yml",
+    ".dir-locals.el",
+    "docs",
+    "rtl/vendor",
+    "scripts",
+  ]
+}

hw/vendor/esl_epfl_cv32e40px/.gitignore

@@ -0,0 +1,20 @@
+TAGS
+*.swp
+*~
+*.o
+*.log
+*.vcd
+*.xml
+*.dbg
+*.wlf
+*.elf
+*.hex
+*.map
+*.out
+*.json
+.build-rtl
+.lib-rtl
+.opt-rtl
+/build
+/Bender.lock
+/Bender.local

hw/vendor/esl_epfl_cv32e40px/.readthedocs.yaml

@@ -0,0 +1,19 @@
+# Configuration file for ReadTheDocs, used to render the CV32E40P User Manual to
+# https://docs.openhwgroup.org/projects/cv32e40p-user-manual
+# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.1
+
+version: 2
+
+#build:
+#  os: "ubuntu-20.04"
+#  tools:
+#    python: "3.9"
+
+# Build from the docs/source directory with Sphinx
+sphinx:
+  configuration: docs/source/conf.py
+
+# Explicitly set the Python requirements
+python:
+  install:
+    - requirements: docs/requirements.txt

hw/vendor/esl_epfl_cv32e40px/.travis.yml

@@ -0,0 +1,118 @@
+# Copyright 2020 ETH Zurich
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+language: cpp
+# run on new infrastructure
+dist: xenial
+sudo: false
+cache:
+  apt: true
+  directories:
+    $RISCV
+    $VERILATOR_ROOT
+  timeout: 1000
+
+# required packages to install
+addons:
+  apt:
+    sources:
+      - ubuntu-toolchain-r-test
+    packages:
+      - gcc-7
+      - g++-7
+      - gperf
+      - autoconf
+      - automake
+      - autotools-dev
+      - libmpc-dev
+      - libmpfr-dev
+      - libgmp-dev
+      - gawk
+      - build-essential
+      - bison
+      - flex
+      - texinfo
+      - python-pexpect
+      - libusb-1.0-0-dev
+      - default-jdk
+      - zlib1g-dev
+      - valgrind
+env:
+  global:
+    - RISCV="/home/travis/riscv_install"
+    - VERILATOR_ROOT="/home/travis/verilator-4.018"
+
+
+before_install:
+  - export CXX=g++-7 CC=gcc-7
+  # setup dependent paths
+  - export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
+  - export LIBRARY_PATH=$RISCV/lib
+  - export LD_LIBRARY_PATH=$RISCV/lib
+  - export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/share/verilator/include
+  - export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/share/verilator/include
+  - export PKG_CONFIG_PATH=$VERILATOR_ROOT/share/pkgconfig
+  # number of parallel jobs to use for make commands and simulation
+  - export NUM_JOBS=4
+  - ci/make-tmp.sh
+  - git submodule update --init --recursive
+
+stages:
+  - download
+  - compile1
+  - compile2
+  - test
+
+jobs:
+  include:
+    - stage: download
+      name: download pulp gcc
+      script:
+        - ci/download-pulp-gcc.sh
+
+    - stage: compile2
+      name: build verilator
+      script:
+        - ci/install-verilator.sh
+    - stage: compile2
+      name: build openocd
+      script:
+        - ci/get-openocd.sh
+
+    - stage: test
+      name: run openocd debug module tests
+      script:
+        - ci/veri-run-openocd-compliance.sh
+    - stage: test
+      name: run riscv tests
+      script:
+        - make -C tb/core firmware-veri-run
+    - stage: test
+      name: run verilator model
+      script:
+        - make -C tb/verilator-model/ all && ./tb/verilator-model/testbench
+    - stage: test
+      name: run riscv-compliance suite
+      script:
+        - export RISCV_PREFIX=riscv32-unknown-elf-
+        - export RISCV_DEVICE=rv32imc
+        - export RISCV_TARGET=ri5cy
+        - export TARGET_SIM=${TRAVIS_BUILD_DIR}/tb/core/testbench_verilator
+        - git clone https://github.com/bluewww/riscv-compliance.git -b target-ri5cy
+        - make -C tb/core verilate
+        - make -C riscv-compliance/ RISCV_ISA=rv32im && make -C riscv-compliance/ RISCV_ISA=rv32imc
+#        - make -C riscv-compliance/ RISCV_ISA=rv32i # this is borked
+
+# extra time during long builds
+install: travis_wait