Use XtalClock as UART source and adapt interrupt binding #123
Workflow file for this run
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| name: CI | |
| on: | |
| pull_request: | |
| branches: | |
| - main | |
| push: | |
| workflow_dispatch: | |
| env: | |
| CARGO_TERM_COLOR: always | |
| GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} | |
| # Cancel any currently running workflows from the same PR, branch, or | |
| # tag when a new workflow is triggered. | |
| # | |
| # https://stackoverflow.com/a/66336834 | |
| concurrency: | |
| cancel-in-progress: true | |
| group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }} | |
| jobs: | |
| # -------------------------------------------------------------------------- | |
| # Cargo check | |
| check-riscv: | |
| runs-on: ubuntu-latest | |
| strategy: | |
| fail-fast: false | |
| matrix: | |
| build: | |
| [ | |
| { chip: "esp32c2", target: "riscv32imc-unknown-none-elf" }, | |
| { chip: "esp32c3", target: "riscv32imc-unknown-none-elf" }, | |
| { chip: "esp32c6", target: "riscv32imac-unknown-none-elf" }, | |
| { chip: "esp32h2", target: "riscv32imac-unknown-none-elf" }, | |
| ] | |
| steps: | |
| - uses: actions/checkout@v4 | |
| - uses: dtolnay/rust-toolchain@v1 | |
| with: | |
| target: ${{ matrix.build.target }} | |
| toolchain: nightly | |
| components: rust-src | |
| - uses: Swatinem/rust-cache@v2 | |
| - name: cargo check | |
| run: cargo check -Zbuild-std=core --target=${{ matrix.build.target }} --features=${{ matrix.build.chip }} | |
| check-xtensa: | |
| runs-on: ubuntu-latest | |
| strategy: | |
| fail-fast: false | |
| matrix: | |
| build: | |
| [ | |
| { chip: "esp32", target: "xtensa-esp32-none-elf" }, | |
| { chip: "esp32s2", target: "xtensa-esp32s2-none-elf" }, | |
| { chip: "esp32s3", target: "xtensa-esp32s3-none-elf" }, | |
| ] | |
| steps: | |
| - uses: actions/checkout@v4 | |
| - uses: esp-rs/xtensa-toolchain@v1.5 | |
| with: | |
| default: true | |
| ldproxy: false | |
| buildtargets: ${{ matrix.build.chip }} | |
| - uses: Swatinem/rust-cache@v2 | |
| - name: cargo check | |
| run: cargo check -Zbuild-std=core --target=${{ matrix.build.target }} --features=${{ matrix.build.chip }} | |
| # -------------------------------------------------------------------------- | |
| # Formatting & Clippy | |
| clippy-riscv: | |
| runs-on: ubuntu-latest | |
| strategy: | |
| matrix: | |
| build: | |
| [ | |
| { chip: "esp32c2", target: "riscv32imc-unknown-none-elf" }, | |
| { chip: "esp32c3", target: "riscv32imc-unknown-none-elf" }, | |
| { chip: "esp32c6", target: "riscv32imac-unknown-none-elf" }, | |
| { chip: "esp32h2", target: "riscv32imac-unknown-none-elf" }, | |
| ] | |
| steps: | |
| - uses: actions/checkout@v4 | |
| - uses: dtolnay/rust-toolchain@v1 | |
| with: | |
| target: ${{ matrix.build.target }} | |
| toolchain: stable | |
| components: clippy | |
| - uses: Swatinem/rust-cache@v2 | |
| - name: cargo clippy | |
| run: cargo clippy --target=${{ matrix.build.target }} --features=${{ matrix.build.chip }} -- -D warnings --no-deps | |
| clippy-xtensa: | |
| runs-on: ubuntu-latest | |
| strategy: | |
| fail-fast: false | |
| matrix: | |
| build: | |
| [ | |
| { chip: "esp32", target: "xtensa-esp32-none-elf" }, | |
| { chip: "esp32s2", target: "xtensa-esp32s2-none-elf" }, | |
| { chip: "esp32s3", target: "xtensa-esp32s3-none-elf" }, | |
| ] | |
| steps: | |
| - uses: actions/checkout@v4 | |
| - uses: esp-rs/xtensa-toolchain@v1.5 | |
| with: | |
| default: true | |
| ldproxy: false | |
| buildtargets: ${{ matrix.build.chip }} | |
| - uses: Swatinem/rust-cache@v2 | |
| - name: cargo clippy | |
| run: cargo clippy -Zbuild-std=core --target=${{ matrix.build.target }} --features=${{ matrix.build.chip }} -- --no-deps | |
| rustfmt: | |
| runs-on: ubuntu-latest | |
| steps: | |
| - uses: actions/checkout@v4 | |
| - uses: dtolnay/rust-toolchain@v1 | |
| with: | |
| toolchain: nightly | |
| components: rustfmt | |
| - uses: Swatinem/rust-cache@v2 | |
| - name: cargo fmt | |
| run: cargo fmt --all -- --check | |
| # -------------------------------------------------------------------------- | |
| # MSRV Check | |
| msrv-riscv: | |
| runs-on: ubuntu-latest | |
| strategy: | |
| fail-fast: false | |
| matrix: | |
| build: | |
| [ | |
| { chip: "esp32c2", target: "riscv32imc-unknown-none-elf" }, | |
| { chip: "esp32c3", target: "riscv32imc-unknown-none-elf" }, | |
| { chip: "esp32c6", target: "riscv32imac-unknown-none-elf" }, | |
| { chip: "esp32h2", target: "riscv32imac-unknown-none-elf" }, | |
| ] | |
| steps: | |
| - uses: actions/checkout@v4 | |
| - uses: dtolnay/rust-toolchain@v1 | |
| with: | |
| target: ${{ matrix.build.target }} | |
| toolchain: "1.76.0" | |
| components: rust-src | |
| - name: cargo check | |
| run: cargo check --target=${{ matrix.build.target }} --features=${{ matrix.build.chip }} | |
| msrv-xtensa: | |
| runs-on: ubuntu-latest | |
| strategy: | |
| fail-fast: false | |
| matrix: | |
| build: | |
| [ | |
| { chip: "esp32", target: "xtensa-esp32-none-elf" }, | |
| { chip: "esp32s2", target: "xtensa-esp32s2-none-elf" }, | |
| { chip: "esp32s3", target: "xtensa-esp32s3-none-elf" }, | |
| ] | |
| steps: | |
| - uses: actions/checkout@v4 | |
| - uses: esp-rs/xtensa-toolchain@v1.5 | |
| with: | |
| default: true | |
| ldproxy: false | |
| buildtargets: ${{ matrix.build.chip }} | |
| version: "1.76.0" | |
| - uses: Swatinem/rust-cache@v2 | |
| - name: cargo check | |
| run: cargo check -Zbuild-std=core --target=${{ matrix.build.target }} --features=${{ matrix.build.chip }} |