Fix ESP32-C3 interrupt/exception handling (#207)

* Fix ESP32-C3 interrupt/exception handling * Use riscv-atomic-emulation-trap 0.2.0
esp-rs · Oct 5, 2022 · af745ac · af745ac
1 parent 5054681
commit af745ac
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Showing 5 changed files with 31 additions and 9 deletions.
diff --git a/esp-hal-common/Cargo.toml b/esp-hal-common/Cargo.toml
@@ -26,7 +26,7 @@ void             = { version = "1.0.2", default-features = false }
 
 # RISC-V
 riscv                       = { version = "0.8.0", optional = true }
-riscv-atomic-emulation-trap = { version = "0.1.1", optional = true }
+riscv-atomic-emulation-trap = { version = "0.2.0", optional = true }
 
 # Xtensa
 xtensa-lx    = { version = "0.7.0",  optional = true }

diff --git a/esp-hal-common/src/interrupt/riscv.rs b/esp-hal-common/src/interrupt/riscv.rs
@@ -445,6 +445,10 @@ pub struct TrapFrame {
     pub gp: usize,
     pub tp: usize,
     pub sp: usize,
+    pub pc: usize,
+    pub mstatus: usize,
+    pub mcause: usize,
+    pub mtval: usize,
 }
 
 /// # Safety
@@ -527,7 +531,7 @@ unsafe fn handle_exception(pc: usize, trap_frame: *mut TrapFrame) {
     }
 
     let mut atomic_emulation_trap_frame = riscv_atomic_emulation_trap::TrapFrame {
-        pc: riscv::register::mepc::read(),
+        x0: 0,
         ra: (*trap_frame).ra,
         sp: (*trap_frame).sp,
         gp: (*trap_frame).gp,
@@ -559,11 +563,12 @@ unsafe fn handle_exception(pc: usize, trap_frame: *mut TrapFrame) {
         t4: (*trap_frame).t4,
         t5: (*trap_frame).t5,
         t6: (*trap_frame).t6,
+        pc: (*trap_frame).pc,
     };
 
     _start_trap_atomic_rust(&mut atomic_emulation_trap_frame);
 
-    riscv::register::mepc::write(atomic_emulation_trap_frame.pc);
+    (*trap_frame).pc = atomic_emulation_trap_frame.pc;
     (*trap_frame).ra = atomic_emulation_trap_frame.ra;
     (*trap_frame).sp = atomic_emulation_trap_frame.sp;
     (*trap_frame).gp = atomic_emulation_trap_frame.gp;

diff --git a/esp-hal-common/src/lib.rs b/esp-hal-common/src/lib.rs
@@ -142,8 +142,11 @@ mod critical_section_impl {
     mod riscv {
         unsafe impl critical_section::Impl for super::CriticalSection {
             unsafe fn acquire() -> critical_section::RawRestoreState {
-                let interrupts_active = riscv::register::mstatus::read().mie();
-                riscv::interrupt::disable();
+                let mut mstatus = 0u32;
+                unsafe {
+                    core::arch::asm!("csrrci {0}, mstatus, 8", inout(reg) mstatus);
+                }
+                let interrupts_active = (mstatus & 0b1000) != 0;
 
                 #[cfg(multi_core)]
                 {

diff --git a/esp-hal-common/src/pulse_control.rs b/esp-hal-common/src/pulse_control.rs
@@ -1045,4 +1045,4 @@ rmt!(
     (1, Channel1, channel1, OutputSignal::RMT_SIG_OUT1),
     (2, Channel2, channel2, OutputSignal::RMT_SIG_OUT2),
     (3, Channel3, channel3, OutputSignal::RMT_SIG_OUT3),
-);
+);
diff --git a/esp32c3-hal/src/lib.rs b/esp32c3-hal/src/lib.rs
@@ -97,7 +97,7 @@ global_asm!(
 .align 6
 
 _start_trap_hal:
-    addi sp, sp, -32*4
+    addi sp, sp, -40*4
 
     sw ra, 0*4(sp)
     sw t0, 1*4(sp)
@@ -129,13 +129,27 @@ _start_trap_hal:
     sw s11, 27*4(sp)
     sw gp, 28*4(sp)
     sw tp, 29*4(sp)
-
-    addi s0, sp, 32*4
+    csrrs t1, mepc, x0
+    sw t1, 31*4(sp)
+    csrrs t1, mstatus, x0
+    sw t1, 32*4(sp)
+    csrrs t1, mcause, x0
+    sw t1, 33*4(sp)
+    csrrs t1, mtval, x0
+    sw t1, 34*4(sp)
+
+    addi s0, sp, 40*4
     sw s0, 30*4(sp)
 
     add a0, sp, zero
     jal ra, _start_trap_rust_hal
 
+    lw t1, 31*4(sp)
+    csrrw x0, mepc, t1
+
+    lw t1, 32*4(sp)
+    csrrw x0, mstatus, t1
+
     lw ra, 0*4(sp)
     lw t0, 1*4(sp)
     lw t1, 2*4(sp)