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Patch typo in debug assist register name and used patched esp-pacs
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JurajSadel committed Aug 19, 2024
1 parent e708dbc commit f35f05c
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Showing 2 changed files with 12 additions and 23 deletions.
14 changes: 7 additions & 7 deletions esp-hal/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -53,13 +53,13 @@ xtensa-lx = { version = "0.9.0", optional = true }
# IMPORTANT:
# Each supported device MUST have its PAC included below along with a
# corresponding feature.
esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true }
esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true }
esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true }
esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true }
esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true }
esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true }
esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true }
esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true }
esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true }
esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true }
esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true }
esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true }
esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true }
esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "69e09d8", features = ["critical-section", "rt"], optional = true }

[target.'cfg(target_arch = "riscv32")'.dependencies]
esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" }
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21 changes: 5 additions & 16 deletions esp-hal/src/debugger.rs
Original file line number Diff line number Diff line change
Expand Up @@ -11,22 +11,11 @@ pub fn debugger_connected() -> bool {
{
use crate::peripherals::ASSIST_DEBUG;
let assist_debug = unsafe { &*ASSIST_DEBUG::ptr() };
#[cfg(feature = "esp32c2")]
{
assist_debug
.core_0_debug_mode()
.read()
.core_0_debug_module_active()
.bit_is_set()
}
#[cfg(not(feature = "esp32c2"))]
{
assist_debug
.c0re_0_debug_mode()
.read()
.core_0_debug_module_active()
.bit_is_set()
}
assist_debug
.core_0_debug_mode()
.read()
.core_0_debug_module_active()
.bit_is_set()
}

#[cfg(not(any(xtensa, riscv)))]
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