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update pac #1357

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merged 1 commit into from
Mar 29, 2024
Merged

update pac #1357

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1 change: 1 addition & 0 deletions esp-hal/CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- All `Instance` traits are now sealed, and can no longer be implemented for arbitrary types (#1346)
- DMA channels can/have to be explicitly created for async or blocking drivers, added `set_interrupt_handler` to DMA channels, SPI, I2S, PARL_IO, don't enable interrupts on startup for DMA, I2S, PARL_IO, GPIO (#1300)
- UART: Rework `change_baud` so it is possible to set baud rate even after instantiation (#1350)
- Update `pac`s with removed suffixes in `int` field names. Use `W1TC` for `int_clr`

### Removed

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16 changes: 8 additions & 8 deletions esp-hal/Cargo.toml
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Expand Up @@ -52,14 +52,14 @@ xtensa-lx = { version = "0.9.0", optional = true }
# IMPORTANT:
# Each supported device MUST have its PAC included below along with a
# corresponding feature.
esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "ed6d18f", features = ["critical-section"], optional = true }
esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32p4 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }
esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "1a96602", features = ["critical-section"], optional = true }

[target.'cfg(target_arch = "riscv32")'.dependencies]
esp-riscv-rt = { version = "0.7.0", optional = true, path = "../esp-riscv-rt" }
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8 changes: 4 additions & 4 deletions esp-hal/src/analog/adc/riscv.rs
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Expand Up @@ -288,7 +288,7 @@ impl RegisterAccess for crate::peripherals::ADC1 {
fn is_done() -> bool {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc.int_raw().read().apb_saradc1_done_int_raw().bit()
sar_adc.int_raw().read().apb_saradc1_done().bit()
}

fn read_data() -> u16 {
Expand All @@ -303,7 +303,7 @@ impl RegisterAccess for crate::peripherals::ADC1 {
// Clear ADC1 sampling done interrupt bit
sar_adc
.int_clr()
.write(|w| w.apb_saradc1_done_int_clr().set_bit());
.write(|w| w.apb_saradc1_done().clear_bit_by_one());

// Disable ADC sampling
sar_adc
Expand Down Expand Up @@ -399,7 +399,7 @@ impl RegisterAccess for crate::peripherals::ADC2 {
fn is_done() -> bool {
let sar_adc = unsafe { &*APB_SARADC::PTR };

sar_adc.int_raw().read().apb_saradc2_done_int_raw().bit()
sar_adc.int_raw().read().apb_saradc2_done().bit()
}

fn read_data() -> u16 {
Expand All @@ -413,7 +413,7 @@ impl RegisterAccess for crate::peripherals::ADC2 {

sar_adc
.int_clr()
.write(|w| w.apb_saradc2_done_int_clr().set_bit());
.write(|w| w.apb_saradc2_done().clear_bit_by_one());

sar_adc
.onetime_sample()
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8 changes: 4 additions & 4 deletions esp-hal/src/analog/adc/xtensa.rs
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Expand Up @@ -347,10 +347,10 @@ impl RegisterAccess for crate::peripherals::ADC1 {
cfg_if::cfg_if! {
if #[cfg(esp32s2)] {
adc.int_clr()
.write(|w| w.adc1_done_int_clr().set_bit());
.write(|w| w.adc1_done().clear_bit_by_one());
} else {
adc.int_clr()
.write(|w| w.apb_saradc1_done_int_clr().set_bit());
.write(|w| w.apb_saradc1_done().clear_bit_by_one());
}
}

Expand Down Expand Up @@ -486,10 +486,10 @@ impl RegisterAccess for crate::peripherals::ADC2 {
cfg_if::cfg_if! {
if #[cfg(esp32s2)] {
adc.int_clr()
.write(|w| w.adc2_done_int_clr().set_bit());
.write(|w| w.adc2_done().clear_bit_by_one());
} else {
adc.int_clr()
.write(|w| w.apb_saradc2_done_int_clr().set_bit());
.write(|w| w.apb_saradc2_done().clear_bit_by_one());
}
}

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72 changes: 39 additions & 33 deletions esp-hal/src/dma/gdma.rs
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Expand Up @@ -105,24 +105,24 @@ impl<const N: u8> RegisterAccess for Channel<N> {
fn clear_out_interrupts() {
#[cfg(not(esp32s3))]
Self::out_int().clr().write(|w| {
w.out_eof().set_bit();
w.out_dscr_err().set_bit();
w.out_done().set_bit();
w.out_total_eof().set_bit();
w.outfifo_ovf().set_bit();
w.outfifo_udf().set_bit()
w.out_eof().clear_bit_by_one();
w.out_dscr_err().clear_bit_by_one();
w.out_done().clear_bit_by_one();
w.out_total_eof().clear_bit_by_one();
w.outfifo_ovf().clear_bit_by_one();
w.outfifo_udf().clear_bit_by_one()
});

#[cfg(esp32s3)]
Self::out_int().clr().write(|w| {
w.out_eof().set_bit();
w.out_dscr_err().set_bit();
w.out_done().set_bit();
w.out_total_eof().set_bit();
w.outfifo_ovf_l1().set_bit();
w.outfifo_ovf_l3().set_bit();
w.outfifo_udf_l1().set_bit();
w.outfifo_udf_l3().set_bit()
w.out_eof().clear_bit_by_one();
w.out_dscr_err().clear_bit_by_one();
w.out_done().clear_bit_by_one();
w.out_total_eof().clear_bit_by_one();
w.outfifo_ovf_l1().clear_bit_by_one();
w.outfifo_ovf_l3().clear_bit_by_one();
w.outfifo_udf_l1().clear_bit_by_one();
w.outfifo_udf_l3().clear_bit_by_one()
});
}

Expand Down Expand Up @@ -155,7 +155,9 @@ impl<const N: u8> RegisterAccess for Channel<N> {
}

fn clear_ch_out_done() {
Self::out_int().clr().write(|w| w.out_done().set_bit());
Self::out_int()
.clr()
.write(|w| w.out_done().clear_bit_by_one());
}

fn is_ch_out_done_set() -> bool {
Expand Down Expand Up @@ -193,7 +195,9 @@ impl<const N: u8> RegisterAccess for Channel<N> {
}

fn reset_out_eof_interrupt() {
Self::out_int().clr().write(|w| w.out_eof().set_bit());
Self::out_int()
.clr()
.write(|w| w.out_eof().clear_bit_by_one());
}

fn set_in_burstmode(burst_mode: bool) {
Expand All @@ -214,26 +218,26 @@ impl<const N: u8> RegisterAccess for Channel<N> {
fn clear_in_interrupts() {
#[cfg(not(esp32s3))]
Self::in_int().clr().write(|w| {
w.in_suc_eof().set_bit();
w.in_err_eof().set_bit();
w.in_dscr_err().set_bit();
w.in_dscr_empty().set_bit();
w.in_done().set_bit();
w.infifo_ovf().set_bit();
w.infifo_udf().set_bit()
w.in_suc_eof().clear_bit_by_one();
w.in_err_eof().clear_bit_by_one();
w.in_dscr_err().clear_bit_by_one();
w.in_dscr_empty().clear_bit_by_one();
w.in_done().clear_bit_by_one();
w.infifo_ovf().clear_bit_by_one();
w.infifo_udf().clear_bit_by_one()
});

#[cfg(esp32s3)]
Self::in_int().clr().write(|w| {
w.in_suc_eof().set_bit();
w.in_err_eof().set_bit();
w.in_dscr_err().set_bit();
w.in_dscr_empty().set_bit();
w.in_done().set_bit();
w.infifo_ovf_l1().set_bit();
w.infifo_ovf_l3().set_bit();
w.infifo_udf_l1().set_bit();
w.infifo_udf_l3().set_bit()
w.in_suc_eof().clear_bit_by_one();
w.in_err_eof().clear_bit_by_one();
w.in_dscr_err().clear_bit_by_one();
w.in_dscr_empty().clear_bit_by_one();
w.in_done().clear_bit_by_one();
w.infifo_ovf_l1().clear_bit_by_one();
w.infifo_ovf_l3().clear_bit_by_one();
w.infifo_udf_l1().clear_bit_by_one();
w.infifo_udf_l3().clear_bit_by_one()
});
}

Expand Down Expand Up @@ -316,7 +320,9 @@ impl<const N: u8> RegisterAccess for Channel<N> {
}

fn clear_ch_in_done() {
Self::in_int().clr().write(|w| w.in_done().set_bit());
Self::in_int()
.clr()
.write(|w| w.in_done().clear_bit_by_one());
}

fn is_ch_in_done_set() -> bool {
Expand Down
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