Refactor SHA to use trait. Implement Digest traits for SHA

esp-hal/CHANGELOG.md

@@ -13,6 +13,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Added touch pad support for esp32 (#1873, #1956)
 - Allow configuration of period updating method for MCPWM timers (#1898)
 - Add self-testing mode for TWAI peripheral. (#1929)
+- Added a `PeripheralClockControl::reset` to the driver constructors where missing (#1893)
+- Added `digest::Digest` implementation to SHA (#1908)
 - Added `debugger::debugger_connected`. (#1961)
 
 ### Changed
@@ -24,6 +26,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Allow DMA to/from psram for esp32s3 (#1827)
 - DMA buffers now don't require a static lifetime. Make sure to never `mem::forget` an in-progress DMA transfer (consider using `#[deny(clippy::mem_forget)]`) (#1837)
 - Peripherals (where possible) are now explicitly reset and enabled in their constructors (#1893)
+- SHA driver now use specific structs for the hashing algorithm instead of a parameter. (#1908)
 - Reset peripherals in driver constructors where missing (#1893, #1961)
 
 ### Fixed

esp-hal/Cargo.toml

@@ -22,6 +22,7 @@ cfg-if                   = "1.0.0"
 critical-section         = "1.1.2"
 defmt                    = { version = "0.3.8", optional = true }
 delegate                 = "0.12.0"
+digest                   = { version = "0.10.7", default-features = false, optional = true }
 document-features        = "0.2.10"
 embassy-futures          = { version = "0.1.1", optional = true }
 embassy-sync             = { version = "0.6.0", optional = true }

esp-hal/src/reg_access.rs

@@ -28,6 +28,7 @@ impl EndianessConverter for NativeEndianess {
 }
 
 /// Use BE for ESP32, NE otherwise
+#[derive(Debug, Clone)]
 pub(crate) struct SocDependentEndianess;
 
 #[cfg(not(esp32))]
@@ -61,7 +62,7 @@ impl EndianessConverter for SocDependentEndianess {
 // It assumes incoming `dst` are aligned to desired layout (in future
 // ptr.is_aligned can be used). It also assumes that writes are done in FIFO
 // order.
-#[derive(Debug)]
+#[derive(Debug, Clone)]
 pub(crate) struct AlignmentHelper<E: EndianessConverter> {
     buf: [u8; U32_ALIGN_SIZE],
     buf_fill: usize,