esp-rs · jessebraham · Mar 14, 2023 · Mar 14, 2023
diff --git a/esp-hal-common/Cargo.toml b/esp-hal-common/Cargo.toml
@@ -36,7 +36,7 @@ embassy-time       = { version = "0.1.0", features = ["nightly"], optional = tru
 embassy-futures    = { version = "0.1.0", optional = true }
 
 # RISC-V
-esp-riscv-rt                = { version = "0.1.0", optional = true }
+esp-riscv-rt                = { version = "0.2.0", optional = true }
 riscv-atomic-emulation-trap = { version = "0.4.0", optional = true }
 
 # Xtensa
@@ -87,5 +87,10 @@ embassy-time-systick = []
 embassy-time-timg0   = []
 
 # Architecture-specific features (intended for internal use)
-riscv  = ["critical-section/restore-state-u8",  "procmacros/riscv", "esp-riscv-rt", "riscv-atomic-emulation-trap"]
+riscv  = ["critical-section/restore-state-u8",  "procmacros/riscv", "esp-riscv-rt", "riscv-atomic-emulation-trap", "esp-riscv-rt/zero-bss"]
 xtensa = ["critical-section/restore-state-u32", "procmacros/xtensa"]
+
+# Initialize / clear data sections and RTC memory
+rv-init-data     = ["esp-riscv-rt/init-data", "esp-riscv-rt/init-rw-text"]
+rv-zero-rtc-bss  = ["esp-riscv-rt/zero-rtc-fast-bss"]
+rv-init-rtc-data = ["esp-riscv-rt/init-rtc-fast-data", "esp-riscv-rt/init-rtc-fast-text"]
diff --git a/esp32c2-hal/Cargo.toml b/esp32c2-hal/Cargo.toml
@@ -31,7 +31,6 @@ embedded-hal-1     = { version = "=1.0.0-alpha.9", optional = true, package = "e
 embedded-hal-async = { version = "0.2.0-alpha.0", optional = true }
 embedded-hal-nb    = { version = "=1.0.0-alpha.1", optional = true }
 esp-hal-common     = { version = "0.7.0",  features = ["esp32c2"], path = "../esp-hal-common" }
-r0                 = "1.0.0"
 
 [dev-dependencies]
 critical-section  = "1.1.1"
@@ -45,7 +44,7 @@ static_cell       = "1.0.0"
 
 [features]
 default              = ["rt", "vectored", "xtal40mhz"]
-direct-boot          = []
+direct-boot          = ["esp-hal-common/rv-init-data"]
 eh1                  = ["esp-hal-common/eh1", "dep:embedded-hal-1", "dep:embedded-hal-nb"]
 rt                   = []
 ufmt                 = ["esp-hal-common/ufmt"]

diff --git a/esp32c2-hal/ld/bl-riscv-link.x b/esp32c2-hal/ld/bl-riscv-link.x
@@ -19,10 +19,7 @@ PROVIDE(MachineExternal = DefaultHandler);
 PROVIDE(DefaultHandler = DefaultInterruptHandler);
 PROVIDE(ExceptionHandler = DefaultExceptionHandler);
 
-/* # Pre-initialization function */
-/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
-   then the function this points to will be called before the RAM is initialized. */
-PROVIDE(__pre_init = default_pre_init);
+PROVIDE(__post_init = default_post_init);
 
 /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
 PROVIDE(_setup_interrupts = default_setup_interrupts);

diff --git a/esp32c2-hal/ld/db-riscv-link.x b/esp32c2-hal/ld/db-riscv-link.x
@@ -19,10 +19,7 @@ PROVIDE(MachineExternal = DefaultHandler);
 PROVIDE(DefaultHandler = DefaultInterruptHandler);
 PROVIDE(ExceptionHandler = DefaultExceptionHandler);
 
-/* # Pre-initialization function */
-/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
-   then the function this points to will be called before the RAM is initialized. */
-PROVIDE(__pre_init = default_pre_init);
+PROVIDE(__post_init = default_post_init);
 
 /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
 PROVIDE(_setup_interrupts = default_setup_interrupts);

diff --git a/esp32c2-hal/src/lib.rs b/esp32c2-hal/src/lib.rs
@@ -12,36 +12,3 @@ pub use self::gpio::IO;
 pub mod analog {
     pub use esp_hal_common::analog::{AvailableAnalog, SarAdcExt};
 }
-
-extern "C" {
-    // Boundaries of the .iram section
-    static mut _srwtext: u32;
-    static mut _erwtext: u32;
-    static mut _irwtext: u32;
-
-    // Boundaries of the .bss section
-    static mut _ebss: u32;
-    static mut _sbss: u32;
-}
-
-#[cfg(feature = "direct-boot")]
-#[doc(hidden)]
-#[esp_hal_common::esp_riscv_rt::pre_init]
-unsafe fn init() {
-    r0::init_data(&mut _srwtext, &mut _erwtext, &_irwtext);
-}
-
-#[allow(unreachable_code)]
-#[export_name = "_mp_hook"]
-#[doc(hidden)]
-pub fn mp_hook() -> bool {
-    if cfg!(feature = "direct-boot") {
-        true
-    } else {
-        unsafe {
-            r0::zero_bss(&mut _sbss, &mut _ebss);
-        }
-
-        false
-    }
-}
diff --git a/esp32c3-hal/Cargo.toml b/esp32c3-hal/Cargo.toml
@@ -33,7 +33,6 @@ embedded-hal-async = { version = "0.2.0-alpha.0", optional = true }
 embedded-hal-nb    = { version = "=1.0.0-alpha.1", optional = true }
 embedded-can       = { version = "0.4.1", optional = true }
 esp-hal-common     = { version = "0.7.0",  features = ["esp32c3"], path = "../esp-hal-common" }
-r0                 = "1.0.0"
 
 [dev-dependencies]
 aes               = "0.8.2"
@@ -49,9 +48,9 @@ ssd1306           = "0.7.1"
 static_cell       = "1.0.0"
 
 [features]
-default              = ["rt", "vectored"]
+default              = ["rt", "vectored", "esp-hal-common/rv-zero-rtc-bss"]
 mcu-boot             = []
-direct-boot          = []
+direct-boot          = ["esp-hal-common/rv-init-data", "esp-hal-common/rv-init-rtc-data"]
 eh1                  = ["esp-hal-common/eh1", "dep:embedded-hal-1", "dep:embedded-hal-nb", "dep:embedded-can"]
 rt                   = []
 ufmt                 = ["esp-hal-common/ufmt"]

diff --git a/esp32c3-hal/ld/bl-riscv-link.x b/esp32c3-hal/ld/bl-riscv-link.x
@@ -19,10 +19,7 @@ PROVIDE(MachineExternal = DefaultHandler);
 PROVIDE(DefaultHandler = DefaultInterruptHandler);
 PROVIDE(ExceptionHandler = DefaultExceptionHandler);
 
-/* # Pre-initialization function */
-/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
-   then the function this points to will be called before the RAM is initialized. */
-PROVIDE(__pre_init = default_pre_init);
+PROVIDE(__post_init = default_post_init);
 
 /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
 PROVIDE(_setup_interrupts = default_setup_interrupts);

diff --git a/esp32c3-hal/ld/db-riscv-link.x b/esp32c3-hal/ld/db-riscv-link.x
@@ -19,10 +19,7 @@ PROVIDE(MachineExternal = DefaultHandler);
 PROVIDE(DefaultHandler = DefaultInterruptHandler);
 PROVIDE(ExceptionHandler = DefaultExceptionHandler);
 
-/* # Pre-initialization function */
-/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
-   then the function this points to will be called before the RAM is initialized. */
-PROVIDE(__pre_init = default_pre_init);
+PROVIDE(__post_init = default_post_init);
 
 /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
 PROVIDE(_setup_interrupts = default_setup_interrupts);

diff --git a/esp32c3-hal/ld/mb-riscv-link.x b/esp32c3-hal/ld/mb-riscv-link.x
@@ -18,10 +18,7 @@ PROVIDE(MachineExternal = DefaultHandler);
 PROVIDE(DefaultHandler = DefaultInterruptHandler);
 PROVIDE(ExceptionHandler = DefaultExceptionHandler);
 
-/* # Pre-initialization function */
-/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
-   then the function this points to will be called before the RAM is initialized. */
-PROVIDE(__pre_init = default_pre_init);
+PROVIDE(__post_init = default_post_init);
 
 /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
 PROVIDE(_setup_interrupts = default_setup_interrupts);

diff --git a/esp32c3-hal/src/lib.rs b/esp32c3-hal/src/lib.rs
@@ -62,29 +62,6 @@ extern "C" {
             static mut _image_drom_size: u32;
         }
     }
-
-    // Boundaries of the .iram section
-    static mut _srwtext: u32;
-    static mut _erwtext: u32;
-    static mut _irwtext: u32;
-
-    // Boundaries of the .bss section
-    static mut _ebss: u32;
-    static mut _sbss: u32;
-
-    // Boundaries of the rtc .bss section
-    static mut _rtc_fast_bss_start: u32;
-    static mut _rtc_fast_bss_end: u32;
-
-    // Boundaries of the .rtc_fast.text section
-    static mut _srtc_fast_text: u32;
-    static mut _ertc_fast_text: u32;
-    static mut _irtc_fast_text: u32;
-
-    // Boundaries of the .rtc_fast.data section
-    static mut _rtc_fast_data_start: u32;
-    static mut _rtc_fast_data_end: u32;
-    static mut _irtc_fast_data: u32;
 }
 
 #[cfg(feature = "mcu-boot")]
@@ -94,21 +71,6 @@ extern "C" {
 // Entry point address for the MCUboot image header
 static ENTRY_POINT: unsafe extern "C" fn() = _start;
 
-#[cfg(feature = "direct-boot")]
-#[doc(hidden)]
-#[esp_hal_common::esp_riscv_rt::pre_init]
-unsafe fn init() {
-    r0::init_data(&mut _srwtext, &mut _erwtext, &_irwtext);
-
-    r0::init_data(
-        &mut _rtc_fast_data_start,
-        &mut _rtc_fast_data_end,
-        &_irtc_fast_data,
-    );
-
-    r0::init_data(&mut _srtc_fast_text, &mut _ertc_fast_text, &_irtc_fast_text);
-}
-
 #[cfg(feature = "mcu-boot")]
 #[link_section = ".rwtext"]
 unsafe fn configure_mmu() {
@@ -178,26 +140,12 @@ unsafe fn configure_mmu() {
 }
 
 #[allow(unreachable_code)]
-#[export_name = "_mp_hook"]
+#[export_name = "__post_init"]
 #[doc(hidden)]
 #[cfg_attr(feature = "mcu-boot", link_section = ".rwtext")]
-pub fn mp_hook() -> bool {
+pub fn post_init() {
     #[cfg(feature = "mcu-boot")]
     unsafe {
         configure_mmu();
     }
-
-    unsafe {
-        r0::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end);
-    }
-
-    #[cfg(feature = "direct-boot")]
-    return true;
-
-    // no init data when using normal boot - but we need to zero out BSS
-    unsafe {
-        r0::zero_bss(&mut _sbss, &mut _ebss);
-    }
-
-    false
 }
diff --git a/esp32c6-hal/Cargo.toml b/esp32c6-hal/Cargo.toml
@@ -34,7 +34,6 @@ embedded-hal-async = { version = "0.2.0-alpha.0", optional = true }
 embedded-hal-nb    = { version = "=1.0.0-alpha.1", optional = true }
 embedded-can       = { version = "0.4.1", optional = true }
 esp-hal-common     = { version = "0.7.0",  features = ["esp32c6"], path = "../esp-hal-common" }
-r0                 = "1.0.0"
 
 [dev-dependencies]
 aes               = "0.8.2"
@@ -50,8 +49,8 @@ ssd1306           = "0.7.1"
 static_cell       = "1.0.0"
 
 [features]
-default              = ["rt", "vectored"]
-direct-boot          = []
+default              = ["rt", "vectored", "esp-hal-common/rv-zero-rtc-bss"]
+direct-boot          = ["esp-hal-common/rv-init-data", "esp-hal-common/rv-init-rtc-data"]
 eh1                  = ["esp-hal-common/eh1", "dep:embedded-hal-1", "dep:embedded-hal-nb", "dep:embedded-can"]
 rt                   = []
 ufmt                 = ["esp-hal-common/ufmt"]

diff --git a/esp32c6-hal/ld/bl-riscv-link.x b/esp32c6-hal/ld/bl-riscv-link.x
@@ -24,10 +24,7 @@ PROVIDE(ExceptionHandler = DefaultExceptionHandler);
    ID: */
 PROVIDE(interrupt0 = DefaultHandler);
 
-/* # Pre-initialization function */
-/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
-   then the function this points to will be called before the RAM is initialized. */
-PROVIDE(__pre_init = default_pre_init);
+PROVIDE(__post_init = default_post_init);
 
 /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
 PROVIDE(_setup_interrupts = default_setup_interrupts);

diff --git a/esp32c6-hal/ld/db-riscv-link.x b/esp32c6-hal/ld/db-riscv-link.x
@@ -24,10 +24,7 @@ PROVIDE(ExceptionHandler = DefaultExceptionHandler);
    ID: */
 PROVIDE(interrupt0 = DefaultHandler);
 
-/* # Pre-initialization function */
-/* If the user overrides this using the `#[pre_init]` attribute or by creating a `__pre_init` function,
-   then the function this points to will be called before the RAM is initialized. */
-PROVIDE(__pre_init = default_pre_init);
+PROVIDE(__post_init = default_post_init);
 
 /* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
 PROVIDE(_setup_interrupts = default_setup_interrupts);

diff --git a/esp32c6-hal/src/lib.rs b/esp32c6-hal/src/lib.rs
@@ -11,64 +11,3 @@ pub use self::gpio::IO;
 pub mod analog {
     pub use esp_hal_common::analog::{AvailableAnalog, SarAdcExt};
 }
-
-extern "C" {
-    // Boundaries of the .iram section
-    static mut _srwtext: u32;
-    static mut _erwtext: u32;
-    static mut _irwtext: u32;
-
-    // Boundaries of the .bss section
-    static mut _ebss: u32;
-    static mut _sbss: u32;
-
-    // Boundaries of the rtc .bss section
-    static mut _rtc_fast_bss_start: u32;
-    static mut _rtc_fast_bss_end: u32;
-
-    // Boundaries of the .rtc_fast.text section
-    static mut _srtc_fast_text: u32;
-    static mut _ertc_fast_text: u32;
-    static mut _irtc_fast_text: u32;
-
-    // Boundaries of the .rtc_fast.data section
-    static mut _rtc_fast_data_start: u32;
-    static mut _rtc_fast_data_end: u32;
-    static mut _irtc_fast_data: u32;
-}
-
-#[cfg(feature = "direct-boot")]
-#[doc(hidden)]
-#[esp_hal_common::esp_riscv_rt::pre_init]
-unsafe fn init() {
-    r0::init_data(&mut _srwtext, &mut _erwtext, &_irwtext);
-
-    r0::init_data(
-        &mut _rtc_fast_data_start,
-        &mut _rtc_fast_data_end,
-        &_irtc_fast_data,
-    );
-
-    r0::init_data(&mut _srtc_fast_text, &mut _ertc_fast_text, &_irtc_fast_text);
-
-    esp_hal_common::disable_apm_filter();
-}
-
-#[allow(unreachable_code)]
-#[export_name = "_mp_hook"]
-#[doc(hidden)]
-pub fn mp_hook() -> bool {
-    unsafe {
-        r0::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end);
-    }
-
-    #[cfg(feature = "direct-boot")]
-    return true;
-
-    // no init data when using normal boot - but we need to zero out BSS
-    unsafe {
-        r0::zero_bss(&mut _sbss, &mut _ebss);
-    }
-
-    false
-}