Synchronous/Asynchronous FT245 FIFO protocol cores

IP-cores written in SystemVerilog for communicating with numerous FTDI chips using FT245 FIFO protocol.

The protocol exists in the two versions: synchronous and asynchronous, and there are two cores proto245s and proto245a to use with the appropriate version. Table with supported FTDI devices (based on the protocol specifications) below.

FTDI Chip	USB Speed	Asynchronous FIFO	Synchronous FIFO
FT245R	FullSpeed	↔️ 1MB/s	❌
FT240X	FullSpeed	↔️ 1MB/s	❌
FT2232D	FullSpeed	↔️ 1MB/s	❌
FT232H	HighSpeed	↔️ 8MB/s	↔️ 40MB/s
FT2232H	HighSpeed	↔️ 8MB/s	↔️ 40MB/s
FT232HP/FT233HP	HighSpeed	↔️ 8MB/s	↔️ 40MB/s
FT2232HP/FT2233HP	HighSpeed	↔️ 8MB/s	↔️ 40MB/s
FT600Q	SuperSpeed	❌	↔️ 200MB/s
FT601Q	SuperSpeed	❌	↔️ 400MB/s
FT602Q	SuperSpeed	❌	↔️ 400MB/s

proto245a core

Implements asynchronous FT245 protocol from the one side and provides RX & TX FIFO interfaces from the other side.

Features:

• configurable RX & TX FIFO size
• configurable RD# & WR# assertion time to adapt to any clock frequency
• flexible clock domains - FSM and FIFOs might share the same clock or use separate clocks

Notes:

• Send Immediate / Wake Up signal (SIWU) tied to inactive state

Core hierarchy

Single clock domain:

proto245a (proto245a.sv)
├── rxfifo (fifo_sync.sv)
│   └── dpram (dpram.sv)
└── txfifo (fifo_sync.sv)
    └── dpram (dpram.sv)

Multiple clock domains:

proto245a (proto245a.sv)
├── rxfifo (fifo_async.sv)
│   └── dpram (dpram.sv)
└── txfifo (fifo_async.sv)
    └── dpram (dpram.sv)

FTDI side access waveforms

From FT2232H datasheet.

FIFOs side access

proto245s core

Implements synchronous FT245 protocol from the one side and provides RX & TX FIFO interfaces from the other side.

Features:

• configurable data size (e.g. 8 bits needed for HS devices, 16/32 bits for SS devices)
• configurable RX & TX FIFO size
• configurable RX & TX burst size - maximum number of words per one read/write burst (optional)
• configurable RX & TX FIFO thresholds - transaction will start only if FIFO is filled below/above the threshold
• configurable pause between transactions
• flexible clock domains - FSM and FIFOs might share the same clock or use separate clocks

Notes:

• FT2xx chips: Send Immediate / Wake Up signal (SIWU) tied to inactive state
• FT60x chips: Byte Enable signals (BE) are not supported at the moment, so, all transactions have to be word aligned

Core hierarchy

Single clock domain:

proto245s (proto245s.sv)
├── rxfifo (fifo_sync.sv)
│   └── dpram (dpram.sv)
├── txfifo (fifo_sync.sv)
│   └── dpram (dpram.sv)
└── txovrbuf (fifo_sync.sv)
    └── dpram (dpram.sv)

Multiple clock domains:

proto245s (proto245s.sv)
├── rxfifo (fifo_async.sv)
│   └── dpram (dpram.sv)
├── txfifo (fifo_async.sv)
│   └── dpram (dpram.sv)
└── txovrbuf (fifo_sync.sv)
    └── dpram (dpram.sv)

FTDI side access waveforms

From FT2232H datasheet.

From FT600Q/FT601Q datasheet.

FIFOs side access

The same as for proto245a core.

Examples

Project	FPGA/Board	FTDI chip	Software
ft2232h_de10lite	DE10-Lite	FT2232H	Python (ftd2xx, pylibftdi, pyusb, ftdi1)

For more details please follow README files inside examples/$PROJNAME$ directories.

Simulation and testing

Environment is built around Python pytest framework - it offers some nice and easy to use tools for test execution control and parametrization out of the box.

Current workflow is based on the pyhdlsim example - sim.py is a wrapper around HDL simulators and test_*.py files contain tests.

Tested on:

• Windows 10, Python 3.8, Modelsim 10.6d
• Ubuntu 20.04, Python 3.8, Modelsim 2020.02

For more details please follow testing README.