Enabled MMCM real number parameter support

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
f4pga · Nov 17, 2020 · 92fc8b6 · 92fc8b6
1 parent b98d374
commit 92fc8b6
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Showing 7 changed files with 35 additions and 25 deletions.
diff --git a/xc/xc7/tests/mmcm/mmcm_buf_basys3_bottom.v b/xc/xc7/tests/mmcm/mmcm_buf_basys3_bottom.v
@@ -40,7 +40,7 @@ mmcme2_test #
 (
 .FEEDBACK   ("BUFG")
 )
-plle2_test
+mmcme2_test
 (
 .CLK        (CLK),
 .RST        (RST),

diff --git a/xc/xc7/tests/mmcm/mmcm_ext_basys3_bottom.v b/xc/xc7/tests/mmcm/mmcm_ext_basys3_bottom.v
@@ -40,7 +40,7 @@ mmcme2_test #
 (
 .FEEDBACK   ("EXTERNAL")
 )
-plle2_test
+mmcme2_test
 (
 .CLK        (CLK),
 .RST        (RST),

diff --git a/xc/xc7/tests/mmcm/mmcm_int_basys3_bottom.v b/xc/xc7/tests/mmcm/mmcm_int_basys3_bottom.v
@@ -40,7 +40,7 @@ mmcme2_test #
 (
 .FEEDBACK   ("INTERNAL")
 )
-plle2_test
+mmcme2_test
 (
 .CLK        (clk),
 .RST        (RST),

diff --git a/xc/xc7/tests/mmcm/mmcm_int_frac_basys3_bottom.v b/xc/xc7/tests/mmcm/mmcm_int_frac_basys3_bottom.v
@@ -39,10 +39,10 @@ wire RST = rst_sr[0];
 mmcme2_test #
 (
 .FEEDBACK           ("INTERNAL"),
-.CLKFBOUT_MULT_F    (16750),
-.CLKOUT0_DIVIDE_F   (16250)
+.CLKFBOUT_MULT_F    (16.750),
+.CLKOUT0_DIVIDE_F   (16.250)
 )
-plle2_test
+mmcme2_test
 (
 .CLK        (clk),
 .RST        (RST),

diff --git a/xc/xc7/tests/mmcm/mmcme2_test.v b/xc/xc7/tests/mmcm/mmcme2_test.v
@@ -21,8 +21,8 @@ output wire [6:0]   O_CNT
 parameter FEEDBACK = "INTERNAL";
 
 // CLKFBOUT multiplier and CLKOUT0 divider (can be fractional)
-parameter CLKFBOUT_MULT_F  = 16000;
-parameter CLKOUT0_DIVIDE_F = 16000;
+parameter CLKFBOUT_MULT_F  = 16.000;
+parameter CLKOUT0_DIVIDE_F = 16.000;
 
 // ============================================================================
 // Input clock divider (to get different clkins)
@@ -55,32 +55,32 @@ MMCME2_ADV #
 .CLKFBOUT_PHASE     (0),
 
 .CLKOUT0_DIVIDE_F   (CLKOUT0_DIVIDE_F),
-.CLKOUT0_DUTY_CYCLE (50000),
-.CLKOUT0_PHASE      (45000),
+.CLKOUT0_DUTY_CYCLE (0.50),
+.CLKOUT0_PHASE      (45.0),
 
 .CLKOUT1_DIVIDE     (32),
-.CLKOUT1_DUTY_CYCLE (53125),
-.CLKOUT1_PHASE      (90000),
+.CLKOUT1_DUTY_CYCLE (0.53125),
+.CLKOUT1_PHASE      (90.0),
 
 .CLKOUT2_DIVIDE     (48),
-.CLKOUT2_DUTY_CYCLE (50000),
-.CLKOUT2_PHASE      (135000),
+.CLKOUT2_DUTY_CYCLE (0.50),
+.CLKOUT2_PHASE      (135.0),
 
 .CLKOUT3_DIVIDE     (64),
-.CLKOUT3_DUTY_CYCLE (50000),
-.CLKOUT3_PHASE      (-45000),
+.CLKOUT3_DUTY_CYCLE (0.50),
+.CLKOUT3_PHASE      (45.0),
 
 .CLKOUT4_DIVIDE     (80),
-.CLKOUT4_DUTY_CYCLE (50000),
-.CLKOUT4_PHASE      (-90000),
+.CLKOUT4_DUTY_CYCLE (0.50),
+.CLKOUT4_PHASE      (90.0),
 
 .CLKOUT5_DIVIDE     (96),
-.CLKOUT5_DUTY_CYCLE (50000),
-.CLKOUT5_PHASE      (-135000),
+.CLKOUT5_DUTY_CYCLE (0.50),
+.CLKOUT5_PHASE      (135.0),
 
 .CLKOUT6_DIVIDE     (112),
-.CLKOUT6_DUTY_CYCLE (50000),
-.CLKOUT6_PHASE      (-270000),
+.CLKOUT6_DUTY_CYCLE (0.50),
+.CLKOUT6_PHASE      (270.0),
 
 .STARTUP_WAIT       ("FALSE")
 )

diff --git a/xc/xc7/yosys/synth.tcl b/xc/xc7/yosys/synth.tcl
@@ -42,7 +42,7 @@ if { [info exists ::env(INPUT_XDC_FILE)] && $::env(INPUT_XDC_FILE) != "" } {
   propagate_clocks
 }
 
-update_pll_params
+update_pll_and_mmcm_params
 
 # Write the SDC file
 #

diff --git a/xc/xc7/yosys/utils.tcl b/xc/xc7/yosys/utils.tcl
@@ -5,18 +5,28 @@
 proc multiply_param { cell param_name multiplier } {
     set param_value [getparam $param_name $cell]
     if {$param_value ne ""} {
-        set new_param_value [expr int(round($param_value * $multiplier))]
+        set new_param_value [expr int(round([expr $param_value * $multiplier]))]
         setparam -set $param_name $new_param_value $cell
         puts "Updated parameter $param_name of cell $cell from $param_value to $new_param_value"
     }
 }
 
-proc update_pll_params {} {
+proc update_pll_and_mmcm_params {} {
     foreach cell [selection_to_tcl_list "t:PLLE2_ADV"] {
         multiply_param $cell "CLKFBOUT_PHASE" 1000
         for {set output 0} {$output < 6} {incr output} {
             multiply_param $cell "CLKOUT${output}_PHASE" 1000
             multiply_param $cell "CLKOUT${output}_DUTY_CYCLE" 100000
         }
     }
+
+    foreach cell [selection_to_tcl_list "t:MMCME2_ADV"] {
+        multiply_param $cell "CLKFBOUT_PHASE" 1000
+        for {set output 0} {$output < 7} {incr output} {
+            multiply_param $cell "CLKOUT${output}_PHASE" 1000
+            multiply_param $cell "CLKOUT${output}_DUTY_CYCLE" 100000
+        }
+        multiply_param $cell "CLKFBOUT_MULT_F" 1000
+        multiply_param $cell "CLKOUT0_DIVIDE_F" 1000
+    }
 }