Disabled BUFG inference by Vivado when synthesizing netlist from fasm…

…2bels Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
f4pga · Aug 17, 2021 · a23ef14 · a23ef14
1 parent 32f6019
commit a23ef14
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/xc/common/utils/vivado_create_runme.py b/xc/common/utils/vivado_create_runme.py
@@ -10,7 +10,7 @@ def create_runme(f_out, args):
 create_project -force -part {part} design design
 
 read_verilog {bit_v}
-synth_design -top {top}
+synth_design -top {top} -bufg 0
 
 write_checkpoint -force design_{name}_pre_source.dcp