drivers: ethernet: stm32: SRAM3 / MPU configuration #16
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Fixes zephyrproject-rtos#29915. Implements the memory layout and MPU configuration for Ethernet buffers for STM32H7 controllers as recommended by ST. 16 KB of SRAM3 are are reserved for this. The first 256 B are for the RX/TX descriptors and configured as strongly ordered, shareable memory. The rest is for RX/TX buffers and configured as non cacheable memory. This configuration is automatically applied for H7 chips if the SRAM3 memory is enabled in the device tree. Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
boa-pe
approved these changes
Jul 14, 2021
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Fixes zephyrproject-rtos#29915.
Implements the memory layout and MPU configuration for Ethernet buffers
for STM32H7 controllers as recommended by ST. 16 KB of SRAM3 are
are reserved for this. The first 256 B are for the RX/TX descriptors and
configured as strongly ordered, shareable memory. The rest is for RX/TX
buffers and configured as non cacheable memory. This configuration is
automatically applied for H7 chips if the SRAM3 memory is enabled in the
device tree.
Signed-off-by: Mario Jaun mario.jaun@gmail.com