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Model clock-domain crossings between transformed-RTL model and endpoints #49

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merged 16 commits into from
Oct 12, 2018

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davidbiancolin
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@davidbiancolin davidbiancolin commented Jul 19, 2018

Associated midas PR: ucb-bar/midas#90. See that PR for more detail.

As for FireSim specific stuff:

  • Adds Platform Configs for building simulators with clock divison between RC and DRAM models
  • Add recipes to run midas synthesizable unittests
  • Adds unittests to scala tests
    Some unrelated changes that could be dropped:
  • Adds an submodule init only mode to build setup.
    • this is a little hack for speeding up setup on millennium. I continue to have problems with the fast install toolchain working -- i need to full install (Should probably open an issue).

Ultimately we probably want to model 1:3 or 1:2 division between Rocket Chip and the DRAM model by default but i'm seeing some weird behavior in the QC-FRFCFS instances that must be addressed before that can even be considered.

@davidbiancolin davidbiancolin changed the title [WIP] Model clock-domain crossings between transformed-RTL model and endpoints Model clock-domain crossings between transformed-RTL model and endpoints Sep 28, 2018
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@zhemao @sagark this is ready for review

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sagark commented Oct 4, 2018

Re: fast-install toolchain, I don't think we expect it to work on millennium. We'd have to have a separate package for that.

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LGTM!

@davidbiancolin davidbiancolin merged commit 41a80ce into dev Oct 12, 2018
@sagark sagark mentioned this pull request Oct 12, 2018
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@davidbiancolin davidbiancolin deleted the multiclock branch July 17, 2019 21:26
nandor pushed a commit that referenced this pull request Oct 18, 2022
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2 participants