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Bump chisel and firrtl (chipsalliance#1232)
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* Misc changes to better enable autoclonetype
* Bump chisel3 and firrtl and SBT to 1.1.1
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jackkoenig authored Mar 1, 2018
1 parent 20a8876 commit 8c6e745
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Showing 10 changed files with 10 additions and 22 deletions.
2 changes: 1 addition & 1 deletion chisel3
2 changes: 1 addition & 1 deletion firrtl
2 changes: 1 addition & 1 deletion project/build.properties
Original file line number Diff line number Diff line change
@@ -1 +1 @@
sbt.version=1.0.4
sbt.version=1.1.1
Binary file modified sbt-launch.jar
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2 changes: 1 addition & 1 deletion src/main/scala/rocket/Frontend.scala
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Expand Up @@ -62,7 +62,7 @@ class Frontend(val icacheParams: ICacheParams, hartid: Int)(implicit p: Paramete
val slaveNode = icache.slaveNode
}

class FrontendBundle(outer: Frontend) extends CoreBundle()(outer.p)
class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p)
with HasExternallyDrivenTileConstants {
val cpu = new FrontendIO().flip
val ptw = new TLBPTWIO()
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2 changes: 1 addition & 1 deletion src/main/scala/rocket/HellaCache.scala
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Expand Up @@ -173,7 +173,7 @@ abstract class HellaCache(hartid: Int)(implicit p: Parameters) extends LazyModul
val module: HellaCacheModule
}

class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends CoreBundle()(p) {
class HellaCacheBundle(val outer: HellaCache)(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = UInt(INPUT, hartIdLen)
val cpu = (new HellaCacheIO).flip
val ptw = new TLBPTWIO()
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2 changes: 1 addition & 1 deletion src/main/scala/rocket/ICache.scala
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Expand Up @@ -81,7 +81,7 @@ class ICachePerfEvents extends Bundle {
val acquire = Bool()
}

class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
class ICacheBundle(val outer: ICache) extends CoreBundle()(outer.p) {
val hartid = UInt(INPUT, hartIdLen)
val req = Decoupled(new ICacheReq).flip
val s1_paddr = UInt(INPUT, paddrBits) // delayed one cycle w.r.t. req
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2 changes: 1 addition & 1 deletion src/main/scala/tilelink/RegisterRouter.scala
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Expand Up @@ -143,7 +143,7 @@ class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle
implicit val p = arg.p
}

class TLRegBundle[P](val params: P, arg: TLRegBundleArg)(implicit p: Parameters) extends TLRegBundleBase(arg)
class TLRegBundle[P](val params: P, val arg: TLRegBundleArg) extends TLRegBundleBase(arg)

class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
extends LazyModuleImp(router) with HasRegMap
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2 changes: 1 addition & 1 deletion src/main/scala/util/HeterogeneousBag.scala
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Expand Up @@ -11,7 +11,7 @@ final case class HeterogeneousBag[T <: Data](elts: Seq[T]) extends Record with c
def length = elts.length

val elements = ListMap(elts.zipWithIndex.map { case (n,i) => (i.toString, n) }:_*)
override def cloneType: this.type = (new HeterogeneousBag(elts.map(_.cloneType))).asInstanceOf[this.type]
override def cloneType: this.type = (new HeterogeneousBag(elts.map(_.chiselCloneType))).asInstanceOf[this.type]

// IndexedSeq has its own hashCode/equals that we must not use
override def hashCode: Int = super[Record].hashCode
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16 changes: 2 additions & 14 deletions src/main/scala/util/Misc.scala
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Expand Up @@ -8,19 +8,7 @@ import chisel3.experimental.{ChiselAnnotation, RawModule}
import freechips.rocketchip.config.Parameters
import scala.math._

class ParameterizedBundle(implicit p: Parameters) extends Bundle {
override def cloneType = {
try {
this.getClass.getConstructors.head.newInstance(p).asInstanceOf[this.type]
} catch {
case e: java.lang.IllegalArgumentException =>
throwException("Unable to use ParamaterizedBundle.cloneType on " +
this.getClass + ", probably because " + this.getClass +
"() takes more than one argument. Consider overriding " +
"cloneType() on " + this.getClass, e)
}
}
}
class ParameterizedBundle(implicit p: Parameters) extends Bundle

// TODO: replace this with an implicit class when @chisel unprotects dontTouchPorts
trait DontTouch {
Expand Down Expand Up @@ -101,7 +89,7 @@ object ValidMux {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits))
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
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