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Actually run InlineInstances pass
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aswaterman committed Feb 3, 2020
1 parent 3a32cf2 commit be33e8d
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Showing 3 changed files with 23 additions and 2 deletions.
7 changes: 7 additions & 0 deletions Makefrag
Original file line number Diff line number Diff line change
Expand Up @@ -16,9 +16,16 @@ CXX ?= g++
CXXFLAGS := -O1
JVM_MEMORY ?= 2G

EMPTY :=
SPACE := $(EMPTY) $(EMPTY)
COMMA := ,

SBT ?= java -Xmx$(JVM_MEMORY) -Xss8M -XX:MaxPermSize=256M -jar $(base_dir)/sbt-launch.jar
SHELL := /bin/bash

FIRRTL_TRANSFORMS := \
firrtl.passes.InlineInstances \

ROCKET_CLASSES ?= "$(base_dir)/target/scala-2.12/classes:$(base_dir)/chisel3/target/scala-2.12/*"
FIRRTL_JAR ?= $(base_dir)/firrtl/utils/bin/firrtl.jar
FIRRTL ?= java -Xmx$(JVM_MEMORY) -Xss8M -XX:MaxPermSize=256M -cp "$(FIRRTL_JAR)":"$(ROCKET_CLASSES)" firrtl.Driver
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9 changes: 8 additions & 1 deletion emulator/Makefrag-verilator
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,14 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot

%.v %.conf: %.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf -faf $*.anno.json -td $(generated_dir)/$(long_name)/
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) \
-o $*.v \
-X verilog \
--infer-rw $(MODEL) \
--repl-seq-mem -c:$(MODEL):-o:$*.conf \
-faf $*.anno.json \
-td $(generated_dir)/$(long_name)/ \
-fct $(subst $(SPACE),$(COMMA),$(FIRRTL_TRANSFORMS)) \

$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN)
cd $(generated_dir) && \
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9 changes: 8 additions & 1 deletion vsim/Makefrag-verilog
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,14 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot

$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)
$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf -faf $(generated_dir)/$*.anno.json -td $(generated_dir)/$(long_name)/
$(FIRRTL) -i $< \
-o $(generated_dir)/$*.v \
-X verilog \
--infer-rw $(MODEL) \
--repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf \
-faf $(generated_dir)/$*.anno.json \
-td $(generated_dir)/$(long_name)/ \
-fct $(subst $(SPACE),$(COMMA),$(FIRRTL_TRANSFORMS)) \

$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
cd $(generated_dir) && \
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