This project aims to provide LED blinking examples for all the FPGA dev boards in the world.
The goal is to provide a quick way to test your new FPGA board and get acquainted with using FuseSoC in your design flow.
Each FPGA board is implemented as a separate FuseSoC target and users are highly encouraged to add support for their any board at their disposal so that we can have a large collection.
This project is available in the FuseSoC base library, so if you have FuseSoC installed, you likely already have this project as well.
To check if it's available run fusesoc core list and check for a core called fusesoc:utils:blinky.
If it's not there, try to run fusesoc library update to refresh the core libraries and look again.
If it's still not there, or if you want to modify the project, e.g. to add support for an additional board, you can add LED to believe as a new core library with fusesoc library add blinky https://github.com/fusesoc/blinky. LED to believe will now be added as a new library and downloaded to fusesoc_libraries/blinky
To build for your particular board, run fusesoc run --target=<board> fusesoc:utils:blinky where <board> is one of the boards listed in the Board support section below.
Alternatively, run fusesoc core show fusesoc:utils:blinky to find all available targets.
There is also a simulation target available to test the core without any hardware. To use this, run fusesoc run --target=sim fusesoc:utils:blinky.
The simulation target has a number of target-specific configuration parameters that can be set. All target-specific parameters goes on the end of the command line (after the core name).
To list all simulation parameters, run fusesoc run --target=sim fusesoc:utils:blinky --help.
The simulation target depends on the vlog_tb_utils core which is found in another library. If you don't already have the fusesoc-cores library in your workspace, you can add it with fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores.
Example: To run four pulses with a simulated clock frequency of 4MHz and creating a VCD file, run fusesoc run --target=sim fusesoc:utils:blinky --pulses=4 --clk_freq_hz=4000000 --vcd.
The default simulator to use is Icarus Verilog, but other simulators can be used by setting the --tool parameter after the run command.
Currently supported simulators for this target are icarus, modelsim and xsim. To use e.g. modelsim run fusesoc run --target=sim --tool=modelsim fusesoc:utils:blinky.
That was fun, wasn't it? And did you know that once you have gotten a LED to blink in this way, you are actually 90% of the way already to run a small SoC with a RISC-V CPU on the same board. Maybe your board is already supported? Or maybe you're up to the challenge of adding support for it. All it takes is to create a 16MHz clock and allocate an output pin to connect a UART. For more info, move on to learn about and run SERV, the world's smallest RISC-V CPU
The following boards are currently supported:
https://www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html
https://www.arrow.com/en/products/tei0001-03-16-c8/trenz-electronic-gmbh
http://www.armadeus.org/wiki/index.php?title=APF27
http://www.armadeus.org/wiki/index.php?title=APF51
Supports the Alchitry Cu, Au, and Au+ boards, plus the Io Element expansion board which can be used by any of the devices. Use the following targets:
- Cu:
alchitry_cu - Cu with Io Element:
alchitry_cu_io - Au:
alchitry_au - Au+:
alchitry_au_plus - Au+ with Io Element:
alchitry_au_plus_io
All .bin files need to be loaded onto the devices using the Alchitry Loader (which is part of Alchitry Labs).
The cores for the Cu are built using IceStorm, and the cores for the Au and Au+ are built with Xilinx Vivado. Since Vivado does not recognize the devices natively, when building for the Au pass the --setup and --build flags. Otherwise, FuseSoC will fail when trying to load onto the device.
https://alhambrabits.com/alhambra/
https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/
http://www.alinx.com/en/index.php/default/content/143.html
https://www.arrow.com/en/products/bemicromax10/arrow-development-tools
This are two variants for this board:
- 15t has ~10K LUTs. Use
--target=cmod_a7_15t - 35t has ~20K LUTs. Use
--target=cmod_a7_35t
https://digilent.com/reference/programmable-logic/cmod-a7/reference-manual
https://github.com/SoCFPGA-learning/Chameleon96
https://fr.aliexpress.com/item/32281130824.html
https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/CrossLink-NXEvaluationBoard
https://shop.trenz-electronic.de/en/TEI0003-02-CYC1000-with-Cyclone-10-FPGA-8-MByte-SDRAM
https://github.com/tomverbeure/cisco-hwic-3g-cdma
https://www.waveshare.com/wiki/CoreEP4CE10
https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=836
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1021
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=1046
Build de10_nano bitstream with project mistral
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=&No=944&PartNo=1
This development board featuring Zynq 7010 was the control card of Ebit E9+
BTC miner.
Note: The Zynq PL on this board doesn't have a reference clock without involving the Zynq PS. To workaround this problem, the onboard 33MHz clock oscillator can be physically bridged to the PL clock input pin. To do this, solder a fine wire from R2340 (the clock output of X8) to the PL clock input on the pad for the missing R1372 near X5.
https://github.com/xjtuecho/EBAZ4205
https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard
http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board
https://repo.or.cz/fpc-iii.git
https://www.nandland.com/goboard/introduction.html
https://www.olimex.com/wiki/ICE40HX1K-EVB
http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx
https://www.crowdsupply.com/1bitsquared/icebreaker-fpga
https://www.robot-electronics.co.uk/products/fpga/icefun.html
https://www.robot-electronics.co.uk/icewerx.html
https://www.xilinx.com/products/boards-and-kits/dk-u1-kcu1500-g.html
https://github.com/machdyne/brot
https://github.com/machdyne/eis
https://github.com/machdyne/kolibri
https://github.com/machdyne/konfekt
https://github.com/machdyne/kuchen
https://github.com/machdyne/minze
https://github.com/machdyne/noir
https://github.com/machdyne/riegel
https://github.com/machdyne/schoko
https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/MachXO2BreakoutBoard
https://www.latticesemi.com/products/developmentboardsandkits/machxo3lfstarterkit
https://shop.trenz-electronic.de/en/TEI0001-03-08-C8-MAX1000-IoT-Maker-Board-8KLE-8-MByte-RAM
https://www.microsemi.com/existing-parts/parts/150789
https://www.microchip.com/en-us/development-tool/mpf300-splash-kit
http://www.myirtech.com/list.asp?id=630
There are two vairants available for NEXYS 2 board
- For Nexys 2-500 : Use
--target=nexys_2_500 - For Nexys 2-1200 : Use
--target=nexys_2_1200
https://digilent.com/reference/programmable-logic/nexys-2/start
https://reference.digilentinc.com/reference/programmable-logic/nexys-4/start
https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum
https://reference.digilentinc.com/reference/programmable-logic/nexys-video/start
https://rhsresearch.com/collections/rhs-public/products/nitefury-xilinx-artix-fpga-kit-in-nvme-ssd-form-factor-2280-key-m https://github.com/RHSResearchLLC/NiteFury-and-LiteFury
http://www.armadeus.org/wiki/index.php?title=OPOS6UL_SP
http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello
https://github.com/ChinaQMTECH/QM_CYCLONE_V/tree/master/5CEFA5F23
This example use mistral toolchain
The Wukong board have two revisions : Artix-7 XC7A100T and Artix-7 XC7A100T-200T . The first revision have the 50 MHz clock on the wrong pin and don't have micro sd.
Targets are Wukong_v1 for revision 1 , Wukong_100t_v2 and Wukong_200t_v2 for revision 2. Those boards can be programmed with openFPGALoader.
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=816
https://wiki.seeedstudio.com/Spartan-Edge-Accelerator-Board/
https://tangnano.sipeed.com/en/
https://www.crowdsupply.com/tinyfpga/tinyfpga-bx
https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/ultra96-v2/
Note: There is no on-board clock for Zynq PL. Therefore, in this example PL clock is generated and supplied from Zynq PS in the block design. Block design tcl script is generated on Vivado 2020.2. If you have an other version of Vivado installation, you should just create and export the block design bd_ultra96_v2.tcl with fabric clock PL0 is enabled and made external.
ULX3S comes in different sizes. The targets ulx3s_45 and ulx3s_85 are defined for different FPGA sizes
http://www.hseda.com/product/xilinx/XC6SLX9COREV1.0/XC6SLX9CORE.htm
https://www.xilinx.com/products/boards-and-kits/zcu102.html
https://www.xilinx.com/products/boards-and-kits/zcu106.html
http://land-boards.com/blwiki/index.php?title=Cyclone_IV_FPGA_EP4CE6E22C8N_Development_Board_USB_V2
https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/
Zybo Z7 comes with two variants of the Zynq SoC. The targets zybo_z7-10 and zybo_z7-20 are defined for different SoC configurations.
